Hi...
At first,
"2. as process shrinking to under 65nm. at-speed test may needed. What make this happen? We can not keep a enough margin to STA? or STA can not model the chip accuratly? or OCV make the corner based STA in-sufficient? "
as tech node lowers, there is more bandwidth for frequency. so eevn higher frequencies can be achieved with loewring the channel length.
while doing STA, OCV, derating factors might provide a robust timing analysis. But at lower technology nodes, impurities, process variations efects are more likely. and there are one to one effects in real time that might degrade your slew rate of the signals in critical paths in real time chip. So, at-speed testing is also equally important.
as the tech node lowering down, due to complexcity stuckat faults alone might not serve the purpose of testing for manufaturing defects.
as the node lowers down, it has impact on area, timing, power, swing etc..
so, a very small process variation might lead to significant effect on the chip performance.
so, equally important to do robust STA (OCV, derating etc) aswell as atspeed testing.
Regards,
sunil budumuru