Argue for STA and at-speed test

[michealwolf]

1. in the past, scan is operate at a much lower frequency. We do not need to test the chip speed(delay). That means the STA margin is large enough, even not one die will have timing issues.
2. as process shrinking to under 65nm. at-speed test may needed. What make this happen? We can not keep a enough margin to STA? or STA can not model the chip accuratly? or OCV make the corner based STA in-sufficient?

What's you opinion?

Thanks.

 

[sunilbudumuru]

Hi...

At first,

"2. as process shrinking to under 65nm. at-speed test may needed. What make this happen? We can not keep a enough margin to STA? or STA can not model the chip accuratly? or OCV make the corner based STA in-sufficient? "

as tech node lowers, there is more bandwidth for frequency. so eevn higher frequencies can be achieved with loewring the channel length.

while doing STA, OCV, derating factors might provide a robust timing analysis. But at lower technology nodes, impurities, process variations efects are more likely. and there are one to one effects in real time that might degrade your slew rate of the signals in critical paths in real time chip. So, at-speed testing is also equally important.


as the tech node lowering down, due to complexcity stuckat faults alone might not serve the purpose of testing for manufaturing defects.

as the node lowers down, it has impact on area, timing, power, swing etc..

so, a very small process variation might lead to significant effect on the chip performance.

so, equally important to do robust STA (OCV, derating etc) aswell as atspeed testing.

Regards,
sunil budumuru

 

[michealwolf]

Thanks very much for you reply.

I'm a little confused.
Please let me ask the question in a different way.
1. It's impossible to do a robust enough STA to avoid at-speed testing in lower node.
The reason is: some impurities can impact timing, and 130nm like node will not? or lower node process delay is much more disperse, make it impossible to make an enough margin when STA.
2. What's you opinion on Statistical STA? How SSTA affect the whole ASIC flow? How SSAT affect design margin(or yield)? I think it may has some relationship with the at-speed test problem.

Thanks