hvt , lvt and svt all have the same area. there is a single layout done and VT layer is used to generate the other versions. This helps the chip level tools to swap the cells of different VT to achieve the timing and power goals that are set.
What do you mean by VT layer? We know metal layers in a layout.
Which cell has lowest dynamic power and why among hvt, lvt and svt cells? What is the ranking in terms of dynamic power for a cell for hvt, svt, lvt?
That layer signifies the Fab people that the oxide layer should be thick.So depending on the Vt layer the silicon dioxide thickness below the poly is varied.