Are these lines usable?

[FalloutBoy]

I have many Xilinx 9572XL CPLD's and what I am wondering - before I embark on a little adventure is:

Are the lines used to program the CPLD usable after programming as IO lines?

Thx in advance.

 

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The datasheet is your friend and will tell you what you need to know.

https://www.xilinx.com/support/documentation/data_sheets/ds057.pdf


But as you didn't start looking there before posting....
Depends if you program via JTAG (dedicated pins) or through a programmer (uses I/O).

 

[FalloutBoy]

https://www.xilinx.com/support/documentation/data_sheets/ds057.pdf


But as you didn't start looking there before posting....
Depends if you program via JTAG (dedicated pins) or through a programmer (uses I/O).[/QUOTE]

Hi, thanks for the response ; I did look at the datasheet but I am very new to CPLD's I have a lot of them because I got them cheap at a close out sale and I have only just begun learning about them, I am aware of JTAG programming which is the method which I was enquiring about as to if you could use the JTAG pins as IO after programming the IC.

I have not yet chosen a direction for programming - although I do have a Xilinx programmer, I want to ensure I start out using a method which allows for the maximum number of IO lines possible that can be used on the IC.

I've looked at the datasheets again but being new to this I don't know what I was supposed to glean from them that would indicate the usability of these lines one way or another.

Thanks in advance for your time.

OOps I think I just saw what you were referring too, I missed it twice while reading:

A5/TDI 15 9 B3 28 TS0 35 29 F4 60
TMS 16 10 A2 29 TS1 36 30 G5 61
A6/TCK 17 11 A1 30

Would indicate that TDI and TCK could be used but not TMS by the looks of it.

 

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TDI, TDO, TCK, and TMS are dedicated pins (I might be wrong, but I think JTAG 1149.1 requires they be dedicated), so no they can't be used as regular I/O.

If you use a standalone programmer like a dataIO programmer that accepts a JEDEC file to program a CPLD then you'll need all those programming pins in the 9500xl.pdf document, those will only be used when programming in the programmer, otherwise they are just normal user I/O.

The figure in the datasheet shows you the JTAG pins being separate from the I/O pins.

- - - Updated - - -

Truthfully I'm not sure what the mechanism is used to detect that the device is being used on a JEDEC programmer as there doesn't seem to be a pin defined for programming, I suspect it has something to do with the Vpp voltage pin 41 (which is Vccint in the datasheet). From the timing diagram it looks like that pin voltage is raised above the 3.3V rail to initiate programming mode.

Regardless you're better off programming it via JTAG.