Archtitecture of Low voltage Amplifier

[mallikarjun]

Hi,

I wanted to design a amplifier with gain of 90dB, bandwidth of 850Mhz, supply voltage of 1.8v and input swing of 0.5V. input common-mode voltage is around 0.8v. Any architecture for this specification would be appriciated.

Thanks in advance

Mallikarjun

 

[maxwellequ]

Usually if you want large gain with a low supply voltage, you must use (at least) a two-stage amplifier. Eventually gain boosting techniques may be used in the first stage.

However the feasibility and choice of architecture depend on a number of requirements:

- Type of load (just capacitive/ just resistive / both)
- Type of feedback (resistive / sw capac.)
- Load value
- The bandwidth that you mention is with which closed loop gain ?
- Does the amplifier need to be stable in the unit gain configuration.
- Differential / single ended output ?
- ...

Regards

 

[rfsystem]

The second pole frequency is defined by the transconductance of the output stage and the load capacitance. If you want to increase the DC gain up to 90dB you have to use a long channel device at the output for a two stage design. That would create a third pole made of gate cap and transconductance of the output stage. So there is a natural conflict. The solution could only be a parallel 2-stage and 3-stage design. I have seen an integrated bipolar design with similar spec at 5V some years ago. But with 0.18u it could possible be realized.

 

[mitchell]

I think you want to do ADC amplifier , so that the speci is 90db , *50MHz , I thinnk you can reference
current-mode amplifer , In more paper . low power /high speed ADC , they use current-mode amp

 

[mallikarjun]

Hi,

* Amplifier closed loop is gain 2.
* fully differential with differential input swing of 1Vpp.
* load is capactive and is around 1pf
* yes, it has to be stable in unity gain feedback.

 

[maxwellequ]

To have f-3dB=850MHz with a gain of 2 the gain-bandwidth product must be GBW=1.7 GHz (I am assuming a feedback factor of 0.5 - if this amplifier is to be used in a sw capacitor circuit this will be lower due to the input cap of the amplifier - situation gets worst). If you want stability in unit gain amplification the second pole must be at a freq larger than f2=3*1.7 GHz = 5.1 GHz....

In a two-stage miller amplifier the second pole is given by f2=1/(2Pi)gm2/CL where gm2 is the transconductance of the output stage. For CL=1pF you have gm2=53 mS, which is a quite impressive value -> LARGE CURRENT.

With this large current, probably the capacitance of the output transistors are comparable to your CL...

Note that if you are going to use the amplifier always to have a gain of 2, the amplifier may not have to be stable in the unit gain configuration. This means that f2=3*850MHz=2.55 GHz which is lower that the previous value (but still quite a "chalenging" value).

Finally another problem is that the large currents that you need will make the gain of your amplifier be low. This happens because when you increase the current, the gm will increase but the r0 of the transistors will decrease faster -> Since the gain of an amplifer depends on gm.r0 terms, it will be low.

Cant you relax the specs????[/code]

 

[mallikarjun]

Dear maxwell,

Sorry, UGB=850MHz and f-3dB=425MHz.
amplifier gain is constant(2). I am also thinking of using two stage miller compensated amplifier, with folded cascode input stage and common source second stage. Your are correct as we increase the current gain of the amplifier will go down because of that I am thinking of using gain booster at the folded cascode first stage. So what is your thought on this
maxwell.

 

[maxwellequ]

Ok, so the requirements are not that crazy. Your solution makes sense. I agree that probably you need to use gain boosting in the first stage. My advice is that you first make the design without it and see how much gain is "missing". As you probably know the gain boosting complicates the frequency compensation due to the poles/zeros introduced, so it is a good solution to go one step at a time.

The signal swing at the output of the first stage is low because of the gain of the second stage. So, probably (depending on the input and output common-modes) you can still use a cascode amplifier (not folded cascode) because the secondary pole is at a higher frequency. You can rapidly analyze if this is possible.

If you are going to use the amplifier always with a gain of 2, you don't need to guarantee stability at the UGB. Basically you only have to guarantee a good phase margin at 425 MHz, i.e. the secondary poles must be at 3*425 to 4*425 and NOT at 3*850 to 4*850.

Finally there are alternatives to the miller compensation in two stage amplifiers, which may give better results. You can check Razavi book on this (it has an explanation and I think it also has the references you should check).

I hope this helps.

Regards

 

[Edward_2288]

Hi maxwellequ

I have some question in regards to f2=3*1.7 GHz = 5.1 GHz --> may I know, how do you get this? what formula did u use? i get a bit confused.

thanks.

To have f-3dB=850MHz with a gain of 2 the gain-bandwidth product must be GBW=1.7 GHz (I am assuming a feedback factor of 0.5 - if this amplifier is to be used in a sw capacitor circuit this will be lower due to the input cap of the amplifier - situation gets worst). If you want stability in unit gain amplification the second pole must be at a freq larger than f2=3*1.7 GHz = 5.1 GHz....

 

[Edward_2288]

Hi since the power supply voltage is 1.8V, i dont think cascode stage or telescopic stage is suitable. am i right? thx

 

[maxwellequ]

Yes, you are probably right, in a telescopic amp there are 5 transistors from VDD to GND and 1.8 V is a bit thigh...

In what concerns the 3* factor, it is a rule of thumb used in the design phase. If you have a two pole system at which you want to apply feedback, you should have the second pole at a frequency ~3 times the closed loop -3dB frequency . This ensures a reasonable phase margin (60-70º or so...).

 

[onderoz]

I think a folded Cascode topology will meet your need. How about the slew rate, power consumption , PSRR,CMRR... are you not limited by these?

 

[onderoz]

It seems that you are to realize a fully differantial amplifier which concludes that you need a CMFB circuit too. However, you must be carefull when you pick up this circuit. That is to say, CMFB may limit your output swing

 

[bastos4321]

For that application you should use a switched capacitor CMF to save power. As about the arquitecture I would prefer an input stage folded cascode with a second stage output. The cascode compensation gives higer bandwith.

Bastos