Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Arbiter design problem?

Status
Not open for further replies.

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
arbiter design

Hi all,

I have two problem when reading the paper from
https://www.siliconlogic.com/pdf/Arbiters_MattWeber_SLE.pdf

[1] Is Arbiter pure comb logic? If yes, shall its comb logic delay be constrained to within one clock cycle?
[2] Shall one request and one grant both hold only one clock cycle?

Best regards,
Davy
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top