you will get the standerd cell verilog simulation library when you purchase the library(*.lib's,p&r libraries,verilog libraries) from the library vendor).you can find those files in the following folder
you will get the standerd cell verilog simulation library when you purchase the library(*.lib's,p&r libraries,verilog libraries) from the library vendor).you can find those files in the following folder
The characterization tool will generate new liberty/timing files, but the functionality won't change and so you could used the same verilog model.
The timing back annotation (sdf) won't change as well.
I did manual timing analysis using nanotime and generated the verilog files manually. just that its clerical and tedious wprk and would have been better if i had any tool..
Sorry, By mistake I wrote Tetramax instead of Nanotime. I did STA of transistor level spice circuits and generated timing report and manually put those details in Verilog libraries.
Tetramax is the tool in which I would use those libraries.