anyone tell me how to generate standard cell verilog ?

[feel_on_on]

verilog standard cell

anyone tell me how to generate standard cell verilog simulation library?

 

[rameshsuthapalli]

hi,

you will get the standerd cell verilog simulation library when you purchase the library(*.lib's,p&r libraries,verilog libraries) from the library vendor).you can find those files in the following folder

${librarypath}/verilog/${library}.v

regards,
ramesh.s

 

[dhaval4987]

hi,

you will get the standerd cell verilog simulation library when you purchase the library(*.lib's,p&r libraries,verilog libraries) from the library vendor).you can find those files in the following folder

${librarypath}/verilog/${library}.v

regards,
ramesh.s

Ramesh, Is it possible to modify the technology parameters or transistor models and regenerate verilog libraries? How to do that?

 

[rca]

The characterization tool will generate new liberty/timing files, but the functionality won't change and so you could used the same verilog model.
The timing back annotation (sdf) won't change as well.

 

[dhaval4987]

Thank you.

But I did not have any characterization tool.

I did manual timing analysis using nanotime and generated the verilog files manually. just that its clerical and tedious wprk and would have been better if i had any tool..

Thanks for the help though!

 

[rca]

How do you generate timing with tetramax, could you explain for my curiousity?
So you Want to transform thé tetramax mode in verilog?

 

[dhaval4987]

@Rca,

Sorry, By mistake I wrote Tetramax instead of Nanotime. I did STA of transistor level spice circuits and generated timing report and manually put those details in Verilog libraries.
Tetramax is the tool in which I would use those libraries.

Sorry for confusion!