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A 78-month old post ... anyway, I just had the same question and would like to share my thoughts.
It is not about language. VCS supports VHDL, Verilog, SystemVerilog, SystemC, mixed-HDL, openVera, too.
I think VCS is a full suite of "Functional Verification Solution", and VCS-MX is merely a "simulator".
VCS-MX is for analyzing, elaborating, compiling and simulating a design and/or testbench. And VCS has much more features (besides a simulation engine), such as: comprehensive coverage, comprehensive assertion techniques, advanced visualization environment, etc. (Details are referred to: **broken link removed**)