Any special considerations for designing a comparator?

[jordan76]

comparator sensitivity simulation

I want to design a high speed comparator(around 1ns@1.2V/150C for 0.15um process).
The max input swing is 100mv,input common voltage is VCC.
The output should be full swing.

Design constraint:speed,power,area

what simulations should I do besides the .dc and .tran simulation to guarantee its first-cut work?

Thanks in advance!

regards,
jordan76

 

[kyrandia]

I think offset and kickback should be consider carefully too.

 

[jordan76]

kyrandia,

Thanks for your reply! I agree with you, but could you tell me something more in detail about how to simulate offset and kickback effect in HSPICE?

regards,
jordan76

 

[kyrandia]

For comparator, the offset mainly come from mismatch. It can't be simulated, but can be calculated. The fab factory should provide you the related parameter.

To simulate the kickback, your input source must not be ideal. These should have impedance.

 

[maxwellequ]

kyrandia is right about the kickback noise simulation. However, in what concerns the offset, he probably forgot that you can (and should) do Monte-Carlo simulations.

 

[jordan76]

Thanks to kyrandia and maxwellequ!

Could anyone give me some simple spice deck examples on the kickback and offset issues? Thanks in advance!

regards,
jordan76

 

[zhaoshibin]

It depends on your application,if you design a comparators in the sub-adc in i.5bit/stage pipelined ADC using RSD,maybe the limits of offset is relaxed much.

 

[chody]

Simulation for kickback noise

Adding the voltage sources to 10k resistor

eyes146@hotmail.com

 

[bigpop]

you also should check the comparator sensitivity. you max input swing is just 100mv, it is not very large.
And also if the input swing is small, the comparator speed will be slow. So it's better use a preamp before your comparator.