Any methods to convert schematic into layout without manual routing? (Cadence Virtuoso)

[royo.oreo]

Hi all,

I am using Virtuoso IC6.1.6 and I have spent the past couple of days trying to find a tutorial to convert a schematic into a layout. My project is a high speed SERDES serial link and I have finally finished all the simulations and I am now ready for layout.

Thing is, I am using schematic view to design my entire project and I am wondering if there is any tutorial to convert my huge design into a layout. I've tried searching through the web for tutorials but most of them are manual routing and manual placements which would not be ideal for my situation.

I tried:
1. Launch -> Layout XL -> Connectivity -> Generate from all sources.
2. Connectivity -> Place as in schematic
3. Routing -> automatic router.

It seems this method is far from ideal since placement is not optimal and the automatic router is not perfect and causes some DRC errors. While I looked through the web, most Layout XL tutorials are mostly manual and it is not suitable for my needs since I will not be able to manually route my entire design. Please let me know if there is anything else I can do!

Thanks for reading.

 

[Dominik Przyborowski]

Virtuoso EXL available in ICADV20 has some features to enable semi-automation of placement and routing, but in general analog layout is a manual work.

 

[royo.oreo]

Virtuoso EXL available in ICADV20 has some features to enable semi-automation of placement and routing, but in general analog layout is a manual work.

Hi Dominik,

Thanks for the reply. Yeah that makes sense, I guess I just have to manually route it or code it in verilog I suppose.

Thanks for the insight.

-roy

 

[timof]

This is a holy grail of EDA - automated analog routing.
Many EDA companies tried to do that, everyone failed (essentially).
As Dominik mentioned, it's still a manual work - especially for high-speed designs.
And especially for advanced (FinFET) nodes.

 

[royo.oreo]

Hi Timof,

Today I learned... I didn't know automated analog routing is the holy grail of EDA. Looks like I really will have to manually route it unfortunately >:'(

Thanks,
Roy

 

[timof]

Hi Timof,

Today I learned... I didn't know automated analog routing is the holy grail of EDA. Looks like I really will have to manually route it unfortunately >:'(

Thanks,

Roy

Have a look at company called Pulsic, and their tool called Animate:

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[dick_freebird]

Assisted or automated routing is needful of supporting views and rules and such. If there is not that support then it's not going to happen. If you haven't got time to route your design I doubt you've got time to do library development bottom-up for the router-friendly base cells.

I have hand routed a 400Mbps burst mode SERDES in 0.5u CMOS and that project ate 3 years of my life. Because tech was so barely capable there was no slack to donate to timing models and unaccounted-for parasitics and any attempts at block level loop synthesis would fail. Had to build my own logic library because stdCellLib FFs could not even self-toggle at main clock rate. Did it all in Spectre and veriloga, timing closure was grinding test vectors through the analog extracted netlist and checking against expect-vectors. And I had a digital guy at the customer feeding me the logic (for me to make hang at speed) and vectors. I "only" had the burst mode CRU and the physical design and the speed tuning and the verification to do. Still took 3 years.

So now it's Gbps and nm but what's really changed?