Any good idea to design a LDO without output capacitor ?

[taofeng]

ldo without capacitor

what is the state of art for this kind of design ?

thanks

 

[transbrother]

without output cap ldo internal power supply

taofeng,

There have been some patents and research to make the LDO without any output caps.

This is one such example:
**broken link removed**

patent no: 6,373,233

 

[caosl]

ldo output capacitors

Capfree LDO is difficult to design with the requirement of low over/undershoot.Stability is not a problem if you make the compensation internal.

Added after 1 minutes:

Additonal, i think in some application of slowly changing load such some Sensor, no cap LDO can be used to supply it.

 

[arghpok]

ldo+output capacitor

There are some good ideas around this topic, but everything depends on what you are willing to sacrifice. capfree ldo's born to make full SoC designs, area and cost efficient chips. Of course, this is not an easy task to accomplish, simply because there are other important topics like transient response, power consumption (quiescent current) that will be degrade using capfree topologies.

Miller-effect on chip capacitor + multistage gain + feedback/forward control are the most used concepts to achieve the best performance in this class of chips. The latest develops around capfree ldo's can be found in the USPAT website (need registration first).

I think that geometric programming has to be used in analog design to optimize physical resources and time, including power management chips.

 

[foxbei]

ldo changing load

i have the same problem. anyone can recommend some low power design paper to me.

 

[arghpok]

fast +ldo +design

look for Rincon-Mora Papers. He had worked a lot with power managent, even his Ph.D. thesis is about LDO's. You can find those papers in his website.

 

[alasliu]

ldo register

his website address

 

[jt_rf]

ldo without output capacitor

hi,

The only idea i could find was a paper from "Milliken". this uses a fast transient loop to combat the transient load regulation problem.

the main problem faced in capless LDO is transiet load regulation spike...which will be few hundreds of millivolts for a current step of say 0-25mA.

the otherway is to better the slew rate at the output of the Error Amplifier which burns a lot of quiescent current.

regards,
JT

 

[rajanarender_suram]

ldo without caps

what is the state of art for this kind of design ?

thanks

The Paper

"Area-efficient linear regulator with ultra-fast load regulation"

uploaded in



is very fast LDO with out o/p cap and also ultra-fast in working which i also implemented and found good

 

[quaternion]

ldo design concepts

Dr Rincon Mora publications:

**broken link removed**

Also you can found most of the referenced papers in Dr Millikan Master of Science here on board

I didn't remember is Dr Millikan Master of Science here or not , but you can get it with some search

check that:



I have also found good patents on

www.freepatentsonline.com

 

[jt_rf]

whats make you a good limited duty officer

Dear rajanarender_suram

I guess the quiescent current should be very high in your implementation. Is that correct?

regards,
JT