Obviously there spikes when using Anded clock with enable signal. In fact this techniques is the worst gating techniques I know.
Try to use another clock related low power techniques. If you keep to use clock gating use the synopsys Design Compiler which can do the task that you are doing since it is Endowed with this featrure.
still doesn't make sense if there is zero delay between those two clocks why do you need to write anything, because output data will follow 60MHZ clock
it is depend upon the what is the data type of the din
if din is bit type then
if (Clk1'event and Clk1 = '1' )then
dout <= din and clk2
its working
and if the din is integer type or any other data type then u can use one clk as clk signal and other one is used as a enable
process(clk1,clk2,din)
if (Clk1'event and Clk1 = '1' )then
if clk2 ='1'then
dout <= din;
end if;
end if;
end process;