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ANDing Clock with Data

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Member level 1
Jun 11, 2007
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if i ANDing the clock with data, does it create any problems ?

example : clk1 = 60 Mhz and clk2 <= 120 mhz

if rising_edge (clk2)
data_out <= clk1 and Din;
end if;

Does the above one is a good way of coding style?

If not, could you suggest the alternate one?

better to use 60 Mhz Clk as a enable..

if Clk120'event and Clk120 = '1' then
if Clk60 = '1' then
dataout <= DataIn;
end if;
end if;

In this case A D-ff with enable will be synthsized.

What are you trying to do??
What is phase delay between those two clocks??
please provide more details

it depends on the timing relation btw the two clocks

phase delay is zero as 6o mhz clock is derived from 120 mhz clock.

since clk2=2*clk1 with null phase difference there is no problem in your code. Problem imerge when there is delays/skew.

My doubt is, i am using clock as enable signal.

clock gating generates spikes,

i am using using clock as enable signal, does it generates any spikes?

Obviously there spikes when using Anded clock with enable signal. In fact this techniques is the worst gating techniques I know.
Try to use another clock related low power techniques. If you keep to use clock gating use the synopsys Design Compiler which can do the task that you are doing since it is Endowed with this featrure.

as your two clocks are synchronous, I think the best way for gating is writing your code in data flow format(anding them together)

still doesn't make sense if there is zero delay between those two clocks why do you need to write anything, because output data will follow 60MHZ clock

I need 2 control signals from clock,one is in phase to the clock and the other one is complement of the first one.

I am using these 2 control signals in data path logic for multiplexing the incoming data.

shall i use the clock as control signal to mux.


ctrl1 ____|------|____|------|____|------|__

ctrl2 ------|____|------|____|------|____|---

if it is control signal I would do something like this

process(clk, reset)
if reset = '1' then
cntr <= '0';
elsif(clk = '1' and clk'event) then
cntr <= not (cntr);
end if;
end process;

in this case you are not occupying extra clock line, and your timing tool will analyze that properly

it is depend upon the what is the data type of the din
if din is bit type then
if (Clk1'event and Clk1 = '1' )then
dout <= din and clk2
its working
and if the din is integer type or any other data type then u can use one clk as clk signal and other one is used as a enable

if (Clk1'event and Clk1 = '1' )then
if clk2 ='1'then
dout <= din;
end if;
end if;
end process;

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