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And gate using pn diodes

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Damomeera

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see the circuit diagram in the following link:

www.asic-world.com/images/digital/gates_and_2rtl.gif

If X = 0 and Y = 0, then both diodes D1 andD2 are forward biased and thus both diodes conduct and pull F low. If X = 0 and Y = 1, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts and thus pulls F low. If X = 1 and Y = 0, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts and thus pulls F low. If X = 1 and Y = 1, then both diodes D1 andD2 are reverse biased and thus both the diodes are in cut-off and thus there is no drop in voltage at F. Thus F is HIGH.
 

albert22

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Commenting on your explanation.
With any input at 0 you will get approx .7v (diode forward drop) at the output. .For both inputs high you get a high on the output pin. In that case the output voltage will be .7v+the lower of the 2 input voltages (up to a max of VCC).
 

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