Analog PLL frequency variation

[Javier1899]

Hello everyone, i have the following problem:

i designed an analog PLL, a basic one. Composed by a PFD-CP, a passive filter, a VCO and a frequency divider (not programable).
The reference frequency is 32.786kHz and the output frequency is 33.5544MHz (N_div = 1024).
The corners of the transient simulation are ok, the frequency synthesized by the circuit is the right one.
We are now testing the chip in the lab but the frequency synthesized is higher, around 37.5MHz. Also the frequency vary linearly with the supply voltage (1.8V).
I did simulations trying to connect all the loads that the circuit have, pads, parastic caps and res, etc... but the simulation continue to synthesize 33.55MHz. And the output frequency do not vary with Vdd variation. I can't explain what is happening.
Any idea/suggestion?

Thanks

 

[erikl]

1. Did you simulate post-layout (on extracted layout)?

2. When the frequency is too high and varying with supply voltage, can you measure the reference frequency? PFD and/or CP output?

 

[Javier1899]

1. Did you simulate post-layout (on extracted layout)?

2. When the frequency is too high and varying with supply voltage, can you measure the reference frequency? PFD and/or CP output?

Hello erikl, thanks for responding.

1. Yes, the corners simulations where of the extracted view.

2. I can measure the reference, and its the right frequency (32.786kHz) all the time. I don't have pins of the other nodes of the PLL (PFD/CP/Filter inputs-outputs), only the reference and the output of the VCO.

 

[crutschow]

Sounds like the loop is not locked and the VCO is running open-loop.

 

[albbg]

Is 37.5 MHz the maximum frequency of the VCO ? if yes check the polarity of the PFD.

However It could also be the level of the RF coming from the VCO output to the PLL RF input too low.

Could you post the circuit ?

By the way, 33.5544MHz/32.786kHz = 1023.43.... (not an integer number)
If the reference frequency is divided by 1 and the RF frequency is divided by 1024 the resulting output frequency is : 33.572864 MHz

 

[D.A.(Tony)Stewart]

If VCO is too high and loop design uses negative feedback correctly, it tells me input frequency is too noisy or too many transitions OR the /1024 counter is not working with null output and VCO is trying to go higher to create a matched frequency same as reference. In either case it is "unlocked or open loop" and V(vco control) is stuck high.

Use Scope on Mixer output PU/PD to prove this and report this plus any other pins you can monitor.

 

[Javier1899]

Sounds like the loop is not locked and the VCO is running open-loop.

Hello crutschow, thanks for responding.

I agree, but i simulate the extracted view and the results are fine. I had tested several chips and all the same behavior, but with a little difference in the generated frequency. I will try to simulate opening the loop to see if the behavior is the same, may be one connection was too weak and breaked in all samples.

Thank you very much.

- - - Updated - - -

Is 37.5 MHz the maximum frequency of the VCO ? if yes check the polarity of the PFD.

However It could also be the level of the RF coming from the VCO output to the PLL RF input too low.

Could you post the circuit ?

By the way, 33.5544MHz/32.786kHz = 1023.43.... (not an integer number)
If the reference frequency is divided by 1 and the RF frequency is divided by 1024 the resulting output frequency is : 33.572864 MHz

Hello albbg, thanks for responding.

No, the maximum frequency of the VCO is around 45MHz.

Here is a schematic of the circuit.

I am sorry, the ref frequency is not 32.786kHz but 32.768kHz. Very sorry, my bad...

Thank you very much.

 

[Javier1899]

If VCO is too high and loop design uses negative feedback correctly, it tells me input frequency is too noisy or too many transitions OR the /1024 counter is not working with null output and VCO is trying to go higher to create a matched frequency same as reference. In either case it is "unlocked or open loop" and V(vco control) is stuck high.

Use Scope on Mixer output PU/PD to prove this and report this plus any other pins you can monitor.

Hello SunnySkyguy, thanks for responding.

I will do that to check this behavior, thank you very much.

 

[albbg]

I don't see the schematic diagram. Could you post it gain ?

 

[D.A.(Tony)Stewart]

the maximum frequency of the VCO is around 45MHz.
the ref frequency is 32.768kHz.

VCO loop filter control voltage will reduce your VCO phase noise which is amplified by the divide ratio , in this case 1024, so your 37MHz VCO will be very noisy. ( More divide ratio more latency, more phase noise)

The VCO control voltage tells me how to debug your design. The frequency error should be simple to correct. YOu can tune the capacitance on the 32.768kHz reference oscillator to tune the VCO locked frequency (x1024) , while the phase jitter is a matter of understanding BODE plots and PID controllers for some fancy tweaking to the spectral noise.

Try posting a photo and the schematic someday when you get a chance and do it 1st time on your next problem.

 

[Javier1899]

<a title="PLL_33.jpg" href="http://obrazki.elektroda.pl/1371860800_1407342168.jpg"><img src="http://obrazki.elektroda.pl/1371860800_1407342168_thumb.jpg" alt="PLL_33.jpg" /></a>

 

[albbg]

OK, the schematic you used for the simulation is correct, but how did you physically implement the filter and how the RF output of the VCO is sent to the PFD (f.i. through a 18-18-18 ohm splitter) ?
I mean: could you post the actually implemented PLL schematic ?