Analog layout query.... pls help me to solve it

[ajaytronic]

Hello Folks,
I have some query related to custom Layout:

1. Why we connect all dummy pattern to Low potential ( VSS or AVSS)
power supply, Why not to highest potential ( VDD or AVDD) power
supply?

2. If a sensitive net ( any High frequency net) passing over dummy
pattern , Will it create any problem?
Should we avoid sensitive net over dummy pattern??

3. As we connect all moscap between DC signal and low potential( VSS
or AVSS) , so all glitches & spikes transfer to this supply ( AVSS) .
Will it affect the biasing of NMOS ?

 

[santhosh.mandugula]

When dummy patterns are connected to VSS it simply acts as gnd or bulk connection and if you connect it to VDD some extra transistors formation will occur.

 

[protonixs]

Hello Folks,
I have some query related to custom Layout:

1. Why we connect all dummy pattern to Low potential ( VSS or AVSS)
power supply, Why not to highest potential ( VDD or AVDD) power
supply?

2. If a sensitive net ( any High frequency net) passing over dummy
pattern , Will it create any problem?
Should we avoid sensitive net over dummy pattern??

3. As we connect all moscap between DC signal and low potential( VSS
or AVSS) , so all glitches & spikes transfer to this supply ( AVSS) .
Will it affect the biasing of NMOS ?

1. dummy devices are not always connected to VSS. PMOS dummies are usually connected to VDD while NMOS are to VSS.

2. dont pass any sensitive signal through dummies or through any device. these devices introduce parasitic to the high speed signal line that might affect its performance.

3. capacitor passes ac signals while it blocks dc ones. the effect on biasing will depend on how you connect the capacitor.

 

[ajaytronic]

I feel my questions are not clear:

I am asking abt dummy metal filling pattern not about dummy devices.

I am expecting more illustrative answer.

Thanks in advance

 

[anades]

As far as dummy metal filling patterns are concerned, connecting them to ground probably increases self capacitance (w.r.t substrate) of the ground level thereby reducing the ground noise.

 

[aryajur]

Sensitive lines over dummy metal pattern can be routed provided consideration is given to the coupling capacitance through the dummy metal.

 

[SP24]

Dummy fill is not always connected to VSS.In the chip level an autofill is done and the fill pattern is left floating.

Before adding dummy fill the sensitive signals should be identified and properly shielded.This way u can reduce the effect of coupling capacitance.

 

[ajaytronic]

Before adding dummy fill the sensitive signals should be identified and properly shielded.This way u can reduce the effect of coupling capacitance.


SP24,
we connect this shielding metal to VSS only and Dummy metal also we connect to VSS, so if dummy metal is connected to VSS, it should not give any trouble......... until we left it for autofilling at foundry level.
Pls give comment if it is not right.[/u]

 

[SP24]

Ajay,

There is no thumb rule that u should connect the dummy fill to GND.
Its the designers call. I am working in 65nm current steering DAC and we left the dummy fill floating.our critical signal's shielding is shorted to GND.
Please go thru the attached document it may give you some idea.

SP24