Analog Layout Considerations for 90nm!

[abhi_123]

Hi All,

Can any1 plz suggest me some specific Analog layout practices for 90nm and below.You know stuff like what more to take care at 90 and 65nm.
I will be greatful for any pdf's .. web links..

Thanks in advance,
Regards,
Abhi

 

[truebs]

it mainly depends on the foundary and the process u are using..

for accurate layout considerations , you must try to find out PDFS provided by the foundaries. They are the best and most reliable answer to your question.

apart from these, one thing i can tell u is the density considerations become increasingly important in these 90/65 nm tech.

 

[andy2000a]

I think , even in 45n ~ 90nm . analog designer never use " min rule" for real design .

as general , we use > x3 min length device

 

[mpkp123]

Hi,
As most of the people has said, it purely depends on the different technologies and the approach of ur company that how u go for a layout.
There are certain things like the metal widht that we generally take more than minimum and the spacing between them also has to be little more.
other than that different devices have different rules in the particular foundry.

 

[vbhupendra]

give attention to current densities and substrate noise.

 

[abhi_4_u]

andy,
One thing , what does it signify that we donot use min L transistors in 90/65nm. Are you trying to imply that even though the tech permits designers use larger values of L ??
And if yes.. Why???
Why then the need to make Analof designs in 90.. why not stick to 130/180nm??

Regards,
Abhi

 

[mpkp123]

Actually or the digital we use the minimum length transistors only but for the analog layout we dont use the minimum length transistors
the reason being the current densities and the parasitics associated with this and the capability of the transistor to with hold the current also(I think so)

 

[deepak242003]

HI Abhi,

As you go below 90 nm, you need to take care of STI stress effect along wiht the lenght of diffusion.
LOD.
for more in for refer net,

 

[erikl]

... even though the tech permits, designers use larger values of L ??

Yes

And if yes.. Why???

For analog circuitry, symmetry and good matching is paramount. The mis-match ratio ~ 1/√(W*L) , (Pelgrom equation), i.e. larger L provides better matching. That's why - in all processes! - for (critical, i.e. exact) analog layout, larger values than min. L are used.

Why then the need to make Analog designs in 90.. why not stick to 130/180nm??
Regards,
Abhi

This decision depends very much on the digital/analog mix of the design. With a large digital part, a smaller process tech. can provide a more economic solution. With a small - say 10..20% - digital part, the smaller process tech. IMHO wouldn't make much sense.