Analog layout/cmos fabrication questions

[sudeeps]

Hello friends,

I have few questions related to cmos layout/fabrication process that I'm unable to find answers to , please help :

1. Why do we have STI ? specially in lower technology nodes compared to larger nodes ?
2. Why do we need to meet minimum density rules ? What's the issue if density is low at some areas causing a groove during cmp ? Why is the planarity needed ?
3. Why requirement to put dummy's at top and bottom more stringent at lower technology node compared to larger nodes?
4. When we draw a transistor , why do we have a large active rectangle and poly over it rather than source/drain active regions and poly ?
5. How do we route current and how do we route voltage?


Please help.

Thanks

 

[sudeeps]

Wish I could get some help

 

[dick_freebird]

STI, shallow trench isolation, is more repeatable and finer
than old-school LOCOS. Packing density is the goal. But
it can come at a cost because the trench and refill can
add higher stresses / strains that make devices sensitive
to local geometry.

Density rules are for lithographic field loading, and at
some extremes of sparseness the aligner may fail to
find an alignable feature. Uneven "loading" leads to
uneven etch rates, thus to uneven device matching.

Planarity is to maximize interconnect uniformity (t)
across underlying topography. Nonuniform features
like thinned steps limit the etch uniformity and the
minimum metal pitch achievable. Depth-of-field
limitations also impact lithography and planar
surfaces are better.

Dummies become more important as your device
geometry approaches the lithography capability.
Especially with strain effects from STI and so on,
end devices are more unlike "center" devices. So
add "throwaway" end devices and make every used
one, a "center" position.

S/D are self-aligned and oversized to the active-area
cut. You need to open the active area to get the
implants. And you need active under the gate between
S & D, but not under gate poly that's routing elsewhere.
Your poposed scheme has no data to make that happen,
but the active area cut is tried and true (to the tune
of 30+ years' worth of CMOS at the lithographic limit
of the day).

Current, voltage, it's still all just metal. You need to
understand your current loop and your voltage reference
return, and the nonideal "contributors" along the way,
and take appropriate measures to enforce behavior.
Some of this is physical design, some of it is circuit
design. Don't have any real rules for you - "be the
ball" is my approach.