Analog design practices and checklists

[Humungus]

I was wandering if we could make a kind of design database with design best practices and checklists.

Companies have this kind of documents from their huge background cummulated during decades.

Also, writing those guidelines and checklists from scratch is not difficult but extremelly time consuming.

What about if we build a database with such information.

For instance, documents form general aspects of design and layout, amplifiers, bandgaps, voltage regulators, ADCs, etc, etc.

Here I attach a good document I found and I will soon upload a list I'm writing for my company. If somebody is afraid of posting directly the document which would identify the company, I suggest to copy the text content directly to the post or create a text file and post it.

This file is avilable at h**p://gaia.ecs.csus.edu/~pheedley/analog_methodology.pdf

 

[hung_wai_ming@hotmail.com]

Your idea looks good.
I will give support once u finish the first version

 

[pfd001]

it is a good idea

 

[leohart]

support

 

[aryajur]

Good idea, maybe you can start a page on Wikipedia, so that its easily updated by all.

 

[walker5678]

Good idea, which will benifit all the analog guys, admire.

 

[Humungus]

Here are the part of the checklist I have ready for now. I still continue working on it. Make your contribution with your previous experience.

•Test structures:
o Are test structure specifications (input, output, operation frequency, load-ing effects, driving capabilities) in accordance with the characteristics of the signal to test and its generator.
o Are all test structures for output signals inserted?
o Are all test structures for input signals inserted?

•Interfacing among blocks:
o Are levels of all signals interfacing different blocks in accordance with the supply voltages of theses blocks?

•Padring:
o Are I/O cells distributed so that bonding onto final package is feasible and reliable?
o Are supply rails of I/O cells in accordance with the signals they receive from outside the chip?
o Are supply rails of I/O cells in accordance with the signals they receive from chip's core?
o Are redundant supply I/Os in accordance with the goal looked for and in the most appropriate place?

•Simulation:
o Has SOA compliance been verified in all transient simulations?

 

[fixrouter4400]

add my 2 cents knowledge

it's all about layout check list based on my experience.

Make sure that all check list are followed in layout design.
# connectivity & antenna check
#metal and poly density check
# placement of connector e.g pins at boundary etc.
#subtrate contacts ( put as many substrate contacts as possible)
#sensitive nets/signals check
#dummy matching and matched transistors, resistors,capacitors check.
#power and ground routing check
#check device or block origin placement refence to 0,0 check

hope this add up

Added after 4 minutes:

more....

# check distance to boundary rule of thumb( used half-rule e.g. metal to metal spacing with adjacent devices or blocks)

 

[iclayout1001]

Thanks Humungus and fixrouter4400, very good comments. Anything else?

 

[carlson]

Good material!