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Why shouldn't it be? You have a matched current sink at
the source, the gate terminal is biased at the same voltage
as what makes the current in the MOS-diode stack, the
only difference is Vds which is pushing the source up a little
as channel shortens.
Were you expecting perfect matching with imperfectly
matched terminal voltages, or something? Make vdd=1.213
and see matching come around.