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1. Error-free DRC run and GDSII tape-out of your own data base, totally based on the fab's/foundry's PDK
2. Your own test pattern generated considering the fab's/foundry's specification re. format and error coverage.
For more info see the fab's/foundry's detailed docu, which always is confidential.
Thanks for the response! Pardon my ignorance If I haven't caught the complete design flow of Analog and Mixed signal IC design. Could you please elaborate a little, like how is the design done? I am sure you don't use any coding, but are you going for Cell placement directly?, What kind of cells will be used? what is the abstraction level? How do you verify the functionality of the design? How do you generate the stimulus/patterns for functional verification? How do you plan for testing manufacturing defects? In format do you communicate your design to the foundry? Thanks in advance!
I think this is too much to be explained in the scope of a forum post, sorry. To learn about this, I'd suggest to read a textbook about Analog and Mixed Signal Design Methodologies; several of those are available. Abstraction level input can be quite different, depending on available tools and the foundry's PDK support, similar is valid for the verification methods and tools. Foundry communication format in most cases is GDSII, as mentioned above.