A
ahmadagha23
Guest
Hi,
I have a vhdl project for xc2s150 -5PQ208. It is created by ISE5.2 and I can Implement it finely with Ise6.2. but when I want to implement the project with ISE10.1 or even ISE9.2, the following errors arise in MAP step:
in ISE9.2: existed IOBs are less than required IOBs (IOB usage:%139)
in ISE10.1: ERROR
ack:1107 - Unable to combine the following symbols into a single IOB
Would you please help me how I can use my project specially for ISE10.1?
regards
Added after 2 minutes:
I only defined and used a signal with "clk40m" name and assaigned it to GCLK pin in UCF file.
I have a vhdl project for xc2s150 -5PQ208. It is created by ISE5.2 and I can Implement it finely with Ise6.2. but when I want to implement the project with ISE10.1 or even ISE9.2, the following errors arise in MAP step:
in ISE9.2: existed IOBs are less than required IOBs (IOB usage:%139)
in ISE10.1: ERROR
ack:1107 - Unable to combine the following symbols into a single IOBWould you please help me how I can use my project specially for ISE10.1?
regards
Added after 2 minutes:
I only defined and used a signal with "clk40m" name and assaigned it to GCLK pin in UCF file.