Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

An advice about glitch

Status
Not open for further replies.

OvErFlO

Full Member level 3
Joined
Dec 7, 2001
Messages
178
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Activity points
1,356
I have a FPGA Xilinx that generate a 20 Mhz clock (sclk) for drive a DAC, now when I trasmit serial data (sdata) from controller to DAC, DAC acquire serial datas on falling edge and on rising edge I observe glitch (I have see on modelsim simulation), the question is :

If I receive a glitch on rising edge, it's possible that my signal on falling edge can't obtain VIL or VOH to identify a 0 or a 1 ???

What can I do to avoid this ?

thanks
 

Iouri

Advanced Member level 2
Joined
Aug 17, 2005
Messages
682
Helped
87
Reputation
174
Reaction score
8
Trophy points
1,298
Activity points
4,814
did you see glitch on the "real" hardware?
 

Resistance

Member level 4
Joined
Dec 24, 2005
Messages
74
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,288
Activity points
2,034
Hi,

First am not clear with the q i will reply with wat i undersatood.

glitches result when there is race condition or skew but on thing dude glitch can trigger the circuit and can take it on a metasatble state ride..

so it would be helpful if u get to root of the prob or explain i will try..

regards
 

tkbits

Full Member level 5
Joined
Dec 4, 2004
Messages
242
Helped
39
Reputation
78
Reaction score
2
Trophy points
1,298
Activity points
2,209
A glitch is detrimental if it's on a clocking signal, as that can create an extra, unwanted clock period.

If it's on a "data" signal, it will be ignored if it occurs after the capturing clock edge, and it is stable long enough (satisfies setup time) before the next capturing clock edge.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top