Amplitude gain control

[Riemann73]

Hello , Currently I'm designing pierce oscillator 96Mhz with amplitude gain control circuit , the use for capacitor C5 was to limit the nmos drain ac variations to keep its bias point until the feedback regulates the loop and the oscillator bias current, the problem is a large degradation happens to the phase noise due to the presence of this cap , my question is why ? and how to deal with this

 

[D.A.(Tony)Stewart]

What are all your design specs?

 

[Riemann73]

Hello , i am using 65nm tsmc and it is supposed to achieve phase noise less than -135 dbc/hz at 1khz with noise floor -166dbc/hz and less than 400us startup and 4mA at maximum is consumed including the output Buffer and i am using C1=C2=18pF and 1.2 supply and i chosed Re(zc) to be 8 times the ESR. The problem is when i tried to lower the cap value to 100fF instead of 10pF the loop can't regulate the amplitude as it starts increasing again.

 

[Riemann73]

I am getting these warnings while running PSS
WARNING (CMI-2682): M5: The bulk-drain junction forward bias voltage (1.38154 V) exceeds `VjdmFwd' = 851.514 mV. The results are now incorrect because the junction current model has been linearized
WARNING (CMI-2682): M7: The bulk-drain junction forward bias voltage (2.3119 V) exceeds `VjdmFwd' = 840.934 mV. The results are now incorrect because the junction current model has been linearized
Note : i'm using ideal components cap/res

 

[Riemann73]

i am simulating the phase noise of crystal oscillator and while running PSS + Pnoise i get these warnings

Note : i don't get them while running transient nor DC.
i think it could be a convergence problem and i don't know how to solve it.

 

[D.A.(Tony)Stewart]

A bode plot ought to tell you why reducing pF fails to perform as you expected.