AMBA APB verification environment using SV

[Ashima 02]

I am looking for AMBA APB'S RTL as I have to write its verification environment using SystemVerilog.

 

[dpaul]

In the simplest form you need to get hold of a APB slave and connect it to your APB BFM (which you have developed in SV). You can then verify master & slave transactions.
Generally ARM, Synopsys provides such slave IPs (if you have the license).
If you are looking for a free one, try opencores.org

 

[Ashima 02]

I am looking for a free RTL code of APB, but unfortunately not getting on opencores or any other site.

How should I proceed?

 

[dpaul]

In the worst case you need to write your own slave model.
But it is not the best practice since your target is to develop an APB verification environment. So using a self developed APB slave might be prone to errors and you cannot guarantee that your verification environment is robust.

Have you looked extensively in the internet?
My google search with the phrase "apb slave verilog code" gives this as a first link: https://www.edaplayground.com/s/example/192
See if you can use the design.sv given in the right-hand window as your slave unit.

If the above is not satisfactory then you need to find a free larger design in which there is an existing APB subsystem (there might be some in GitHub or Opencores). From there stip-off an APB slave and use it.