altium - bus slice duplicate error

[vixo]

Hi, I've made a multisheet design in altium, but on compiling I get some errors - Duplicate Bus Names Bus Slice. My design has a top sheet(sheet1), which contains four subsidiary sheets(sheet2), and each of those four sheets contain sixteen copies of a third sheet(sheet3) - hope that's clear.

The error seems to be occurring because the four sheet2s have a bus inside them, and when that bus is duplicated it isn't automatically renamed something which distinguishes it from the other sheet2s - Im guessing this because I get the error three times, so the first instance the bus is named and the further three times the sheet is duplicated creates errors. If i increase the number repeats to 5, i then get four errors. These are the only errors I get, so all the nets and components have been renamed ok.

The top sheet also contains a net and this causes no problems, so I suppose the naming of the nets works ok. The project net identifier scope is set to automatic, and seems to have defaulted to hierchical as this option give the same errors.

anyone have any idea why this is happening?

 

[ArticCynda]

A bus, just like a signal harness, is only a schematic element that aims at improving the readability of your schematics. In Altium, they're defined as a group of nets which should automatically be assigned unique names when you duplicate a schematic in a number of sub sheets.

Can you post a few screenshots of your design so we get a better idea of what you're trying to do?

 

[vixo]

no problem. Here are three pictures

the top sheet far view


the top sheet close so you can see the repeat sheet2


inside sheet2 where you can see the 2 buses that are causing the errors and the repeat sheet3

 

[ArticCynda]

Aside from a rather odd layout, I notice you're pulling lines straight in and out of a bus. This is most likely where Altium sees a problem. The interfacing between a single wire and a bus (a collection of wires) is done though a "bus tap", a 45° piece of wire you'll find in your schematic toolbox.

 

[vixo]

ah yes, i noticed that the other day after I posted. I have now changed the schematics so all bus to wire connections have a bus entry, but the problem still stays the same!

Any recommendations regarding the layout would be also appreciated

 

[ArticCynda]

I noticed a few other weird things yes. For example in your last schematic, you define 2 separate buses (they're crossing each other without a dot), and connecting 17 select lines and 16 cathode lines to them. But these lines do not leave the bus anywhere else, meaning they'll essentially remain unconnected in the design.

What I assume you're trying to do is grouping the 17 select lines together and leading them to Repeat (test point), however you can't do that with a bus as a whole. Instead, you want to use a signal harness to group them together and then connect this harness to other blocks.

 

[vixo]

hmm I'm following the steps outlined in this video - https://www.youtube.com/watch?v=dYgvRCrVeOI as far as I can see I'm doing everything the same!

 

[vixo]

what I want is to send 1 of each of those 16 different lines to each repeat. From the altium page on signal harnesses -

Wires are used to represent an electrical connection between points, buses are used to represent a group of related signals which are identified by a specific naming convention.
Signal Harnesses on the other hand, involve the logical grouping of multiple signals including both wires and buses/QUOTE]

since I want to group together signals of the same type rather than group buses and nets, shouldn't I be using a bus rather than a signal harness?

 

[ArticCynda]

In that case a bus would be better than a signal harness yes. Make sure that you define the bus properly, then it should work the way you expect.

I haven't tried including these named buses in multi sheet schematics, so I'm not sure how they're being handled if you duplicate the same sheet multiple times.

 

[vixo]

ahh, I actually solved the problem - it seems that I don't need a bus at all! For example if I just have nets labelled selectx1, selectx2, etc. and a net attaching to a repeat port labelled selectx, it seems to work fine. I have a different problem now, but I suppose that's another question for another thread

thanks for your help!

 

[Manheulles]

If you're using a harness, add the harness name to the wire nets attached to the harness with a dot in between:

HarnessName.NetName