Altera I/O Buffers Instantiation

[upal]

Hello
I am writing code in vhdl for altera for my design.I synthesized a output from quartusii tool and got a code containing i/o buffers for all top level inputs and outputs.Can anyone tell do i need to write this i/o buffers while writing the code.
If no please can u explain.

Thanks in advance
Regards
Upal

 

[Brownout]

I don't understand your question. I/O buffers are nothing more than impedance "transformers" and do not require any special code to work. If you have addressable cores in your design that are connected at the top level using I/O buffers, you just write to the core addresses, and your design takes care of the I/O.

 

[TrickyDicky]

Are you talking about using the registers inside the IO buffers? or are you talking about driving high impedance on an inout port when you need to read a value on it?

 

[FvM]

I synthesized a output from quartusii tool and got a code containing i/o buffers for all top level inputs and outputs.

You got it in the gate level netlist, but you didn't write it in your code? Yes that's normal operation. Usually you don't need to place low level I/O primitives in FPGA designs. You have other ways to specify the I/O features, the Pin Planner tool or the Asignment Editor. That's different from ASIC design, I think.

 

[upal]

Thanks to all.
Actually i am using GHDL as my simulation tool.So in that case do i have to instantiate i/o buffer primitives in my code.I am actually trying to get maximum optimization and that is the reason i am coding with low level primitives.I am confused whether to instantiate the i/o buffers also or not.
Thanks in advance.

 

[TrickyDicky]

Using low level primitive often does not give the maximum optimisation. The synthesisors are better at optimisation than humans.