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Altera FPGA pwoer-up pins state

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sherif123

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I face the following problem. When my altera FPGA power up, the i/o pins have out logic high (voltage level 3 volts), then after the bit file is loaded from the EPCS rom, the pins will have the required values according to the operation. This affects the system that is controlled by the FPGA because some controls should not be high at the start up. The FPGA as I think takes 0.5s to be programmed. The pins stays at 3 volts during this time.
I searched but could not find any useful information about the default state of the pins during power-up.
Power down resistors at the controlled system don't work.
Thanks
 

The behaviour is surely exactly specified in the datasheet. You didn't mention a specific Altera FPGA family, but all Altera FPGA have week pull-up for unconfigured I/O pins.

A pull-down resistor will always solve the problem, but it must be dimensioned appropriately. For example, in case of Cyclone III family, it must be as low as 1k or even 470 ohm to achieve LVTTL low level safely over the expectable type variations.

A straightforward solution is to use exclusively active low level for all critical signals.
 

The behaviour is surely exactly specified in the datasheet. You didn't mention a specific Altera FPGA family, but all Altera FPGA have week pull-up for unconfigured I/O pins.

A pull-down resistor will always solve the problem, but it must be dimensioned appropriately. For example, in case of Cyclone III family, it must be as low as 1k or even 470 ohm to achieve LVTTL low level safely over the expectable type variations.

A straightforward solution is to use exclusively active low level for all critical signals.
Cyclon 3 family
"but all Altera FPGA have week pull-up for unconfigured I/O pins" I mean the configured pins not the unused ones.
 

You didn't think. All pins are unconfigured after power-on.
 

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