sherif123
Member level 3
I face the following problem. When my altera FPGA power up, the i/o pins have out logic high (voltage level 3 volts), then after the bit file is loaded from the EPCS rom, the pins will have the required values according to the operation. This affects the system that is controlled by the FPGA because some controls should not be high at the start up. The FPGA as I think takes 0.5s to be programmed. The pins stays at 3 volts during this time.
I searched but could not find any useful information about the default state of the pins during power-up.
Power down resistors at the controlled system don't work.
Thanks
I searched but could not find any useful information about the default state of the pins during power-up.
Power down resistors at the controlled system don't work.
Thanks