mohd_ind00
Junior Member level 3
Hi All,
I am using Altera cyclone device EP1C6Q240C7. I am able to program and implement the design and it is working.
I have implemented the DPRAM in device and using CLK0 & CLK1 pins of FPGA as two seperate clock for DPRAM. But i analyze the clock is not getting enabled, b'coz Compilation warning showing it is undefined clock.
I don't know how to enable the clock in QuartusII software?
If anybudy knows pl reply.
Thanks
Regards
I am using Altera cyclone device EP1C6Q240C7. I am able to program and implement the design and it is working.
I have implemented the DPRAM in device and using CLK0 & CLK1 pins of FPGA as two seperate clock for DPRAM. But i analyze the clock is not getting enabled, b'coz Compilation warning showing it is undefined clock.
I don't know how to enable the clock in QuartusII software?
If anybudy knows pl reply.
Thanks
Regards