Altera cyclone FPGA clock enable issue in QuartusII software

[mohd_ind00]

Hi All,

I am using Altera cyclone device EP1C6Q240C7. I am able to program and implement the design and it is working.

I have implemented the DPRAM in device and using CLK0 & CLK1 pins of FPGA as two seperate clock for DPRAM. But i analyze the clock is not getting enabled, b'coz Compilation warning showing it is undefined clock.

I don't know how to enable the clock in QuartusII software?

If anybudy knows pl reply.

Thanks

Regards

 

[Renjith]

@ltera cyclone FPGA clock enable issue in QuartusII software

Hi Mohd,
i've not used QuartusII S/W, but i feel this is a generic issue. try to define ur clock signal in the Constrains editor.

 

[cube007]

@ltera cyclone FPGA clock enable issue in QuartusII software

Hello,

CLK0 – CLK3 are inputs for clock signals or normal inputs. Normally they don’t have to be enabled. Quartus is checking this automatically, that’s why it is printing out that there is an undefined clock.

Did you simulate your design with ModelSim? That’s the best way to check your design. You can also route the input CLK0 and CLK1 to different outputs pins to measure if the clock is coming through.


Bye,
cube007