@ltera cyclone FPGA clock enable issue in QuartusII software
Hello,
CLK0 – CLK3 are inputs for clock signals or normal inputs. Normally they don’t have to be enabled. Quartus is checking this automatically, that’s why it is printing out that there is an undefined clock.
Did you simulate your design with ModelSim? That’s the best way to check your design. You can also route the input CLK0 and CLK1 to different outputs pins to measure if the clock is coming through.
Bye,
cube007