Possibly. You need to consider what is important given your application. Is the FIFO slow relative to whatever is reading it (i.e. slow UART FIFO + fast CPU)? If so, it probably doesn't matter. If the data rate is high, then perhaps it does matter. Perhaps a count register would be better than an single empty flag. If the rate is very fast, i.e. only likely to be a cycle or two delay, then you could just drive hready. Alternatively, depending upon the width of the FIFO data and bus, you could combine the empty flag and fifo data.