[AHB] What signal of AHB-Lite might be connected to FIFO's EMPTY output?

[ivlsi]

[AHB] What signal of AHB-Lite should be connected to FIFO's EMPTY output?

Hi All,

I need to connect a regular Sync FIFO as a Slave on AHB-Lite bus.

Where should I connect FIFO's EMPTY signal? It seems connecting it to ~HREADY signal is a bad idea...

Thank you!

 

[jbeniston]

Yep, it's a bad idea, because you can lock the bus up for an arbitrary time. Probably should have a status register that can be read to see if the FIFO contains data.

 

[ivlsi]

What about connection the FIFO EMPTY signal to HRESP or HSPLIT? Probably connecting to HSPLIT is better...

 

[jbeniston]

There's no hsplit in AHB-lite.

 

[ivlsi]

Okay, in case it's a Full AHB bus, could then the FIFO EMPTY be connected to HSPLIT? Is there a better connection for this signal?

 

[Nandy]

You can create another AHB address for empty signal polling. So FIFO data write uses one AHB address(Or maybe a serial of addresses), polling EMPTY signal uses another AHB address.

 

[ivlsi]

I see, but "polling" is not a part of AHB protocol...
So, should status of the EMPTY signal be read each time before reading a value from FIFO? It seems it would reduce by twice the bandwidth of FIFO in term of Reads... I mean, in order to read 4 values from FIFO, should 8 Read Accesses be performed (ReadEmptyStatus->ReadFIFOValue->ReadEmptyStatus->ReadFIFOValue->...)?

 

[jbeniston]

Possibly. You need to consider what is important given your application. Is the FIFO slow relative to whatever is reading it (i.e. slow UART FIFO + fast CPU)? If so, it probably doesn't matter. If the data rate is high, then perhaps it does matter. Perhaps a count register would be better than an single empty flag. If the rate is very fast, i.e. only likely to be a cycle or two delay, then you could just drive hready. Alternatively, depending upon the width of the FIFO data and bus, you could combine the empty flag and fifo data.

 

[ivlsi]

Connection of FIFO FULL signal to HREADY would be okay? Will it not stuck the bus? The HREADY is equal to WAIT, so the bus will be stuck until at least one value from FIFO be read...

 

[jbeniston]

Yes, it would lock up the bus. If you know that the FIFO is likely to have data in a cycle or two, maybe that is OK. If you don't, then it's probably not a good idea.

 

[ivlsi]

So, how to handle FIFO FULL signal from a Slave on AHB bus?