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In a flip flop based design, when considering the clock period, we need to consider three aspects
1. Clock to Q delay.
2. Time taken by logic
3. Setup time
In a FF-based design Clock-to-Q delay and setup time are overheads and need to be addressed at all stages of the design. Therefore, if you try to reduce the clock period simply by reducing the time taken by logic, you will see at one point of time the overheads mentioned above become significant contributing factor to the higher clock rates.
In a latch-based design however, that overhead is paid for only once. Therefore, we can achieve higher clock speeds. Also there is a phenomenon called "time-borrowing". In this case, if one stage cannot finish its operation on time, then a certain amount of time can be borrowed from the subsequent stages, something that cannot be acheived in a FF based design.
As u know latches are level triggered and ffs are edged triggered, thus latches can easily be used in Asynchronous design. An Asynchronous design where clock is not used, it uses handshaking between various logic blocks. Thus it is more faster than synchronous design.
well, here some basic digital questions in attached document.