Advantages Disadvantages of High freq for ASICS

[vikramc98406]

disadvantages of pll

Can anyone give me Advantages Disadvantages of High freq for ASICs.

Many devices have low crystal oscillator and PLL on chip which does frequency multiplication.

why is this required?

 

[gliss]

disadvantages of crystal oscillator

You need these devices for synchronization purposes basically. There can only be so much clock skew throughout the chip. The highly the clock frequency the higher the chip performance but also there is higher power consumption and a more complex clock network.

 

[vikramc98406]

disadvantage crystal oscillator

I understand if the frequency of ASIC is high, power consumption will be high.


Let me reframe my question,

Many devices uses on chip PLL, to divide, multiply for the input Low frequency given to chip.

when multiplied, frequency is the device frequency

My question is, why cant we give device frequency itself to chip instead of multiplying by PLL block.

 

[korgull]

disadvantage of high frequency

My question is, why cant we give device frequency itself to chip instead of multiplying by PLL block.

For starters, it is easier in a sense to use a crystal oscillator to generate your clock which probably will not go as high in clock frequency as you would like to. A quick google search will turn up some crystal oscillators that go up to 2 GHz, but I am not certain they go much higher. So, in this case, if you want a compact circuit, you put some sort of "low" frequency oscillator on the circuit and multiply the clock to generate what you want. In addition, it is also likely that you would like to have stability in the clock signal, hence, a good VCO (voltage controlled oscillator) will be designed.

The trick is getting a quick lock on the PLL. While this may be ok for low frequency clocks, once you start desiring 10's of GHz, a good PLL designer is required.

 

[shiv_emf]

Can anyone point me to good pll design document ?

How do u multiply clock frequency ? or how do u get different clock frequencies with single freq?

 

[korgull]

Can anyone point me to good pll design document ?

How do u multiply clock frequency ? or how do u get different clock frequencies with single freq?

You sort of answered your first question as you multiply a clock frequency with a PLL. If you want to get multiple clock frequencies from there, just attach a clock divider to it. I've never seriously designed a PLL, so I can't help you there other than to look at your college textbooks. IEEE Explore should turn up a few good papers on the subject as well.

 

[kvingle]

Routing clock signals of high frequency on PCB introduces various signal integrity issues and is very difficult .Power consumption is also considerably high.
This is another one major advantage of having internal chip multiplication of clock signal.