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advanced timing constraints

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GiuseppeLaPiana

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Hi all,

I am having some problems with DDR timing constraints.

So far I have:

create_clock -name virt_clock -period 6
create_clock I_DQS_90 -period 6
create_clock I_SYS_CLOCK -period 6

set_input_delay .7 -max -clock [get_clock virt_clock] -add_delay
set_input_delay .7 -max -clock [get_clock virt_clock] -clock_fall -add_delay
set_clock_latency 1.5 I_DQS_90

I_DQS_90 is the capture strobe transmitted from the dram module, it clocks rising and falling edge flip flops

The virt_clock represents an edge aligned clock with the data. .7 ns delay is the maximum delay data can have from the edge of the virtual clock.

The problem is that rising edge data is being launched on the falling edge of the virt clock, and latched in on the rising edge of the 90 degree shifted clock, the falling edge data is launched on the rising edge of the virtual clock and captured on the falling edge of the 90 degree shifted clock.

It should be rising edge data launched rising edge virt_clock and captured on rising edge 90 clock. Vice versa falling edge. Anyone have an idea to fix this?
 

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