Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ADS Layout output results

Status
Not open for further replies.

jdstavares

Junior Member level 2
Joined
Nov 3, 2022
Messages
22
Helped
1
Reputation
2
Reaction score
0
Trophy points
1
Activity points
167
Hi eveyone.

I finished the layout, and now I was simulating the schematic from the layout. And the results are really different, from the schematic, which I had efficiency of 30%, and now for the final results the efficiency is basically 0. Moreover, the output is also pretty bad compared with the schematic. I know that some differences may happen, during the conversion but not as huge as this...

I saw the substrate and everything and it seems like everything is well defined, but obviously there's some kind of parameter which is not well defined...

Can anyone help me?
 
Last edited:

Archive your project with used models and post it here as zipped.
Don't zip the project directory itself, archive the project then zip it.
 
Your equations essentially are wrong. You typed the powers in dBm but you don't know the impedance so you cannot obtain the power in this way. Correct your equations and try one more time.
Not : dBm functions assumes that the Load Impedance is 50 Ohm otherwise is noted. Because ADS uses Voltages while it computes dBm. See its help..
 

Attachments

  • DisplayData.pdf
    18 KB · Views: 140

Well, I rewrite them and here is the result:
The same is happening...

And what is the vout, you are obtaining? Because my vout from the schematic is ~800 mV and here ~3.6E-5 V.
1668313518248.png

1668313458860.png
 

Yes, it was indeed one port that wasn't defined correctly.
Well I'm having now eff of ~0.3% and vout ~145 mV
I want to perform now the optimization, because in the schematic I had ~800 mV and wanted, if possible to achieve a similar output or at least half of it. And ocr increase de eff.... But whenever I try to do it, this error appears:

And I don't understand exaclty what is wrong...

1668527157318.png
 
Last edited:

Well I guess the true problem is still due to the ports... I'm defining like this now, and the eff increased from 0.3 to 0.8% still really low
1668543380928.png
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top