Hi,
when you talk about 'ring' you should specify which ring you mean: pad ring (metall wires which sypply of IO cells rather then core cell) or Core ring (metall rings that sypply core std cells)
If you talk about Pad ring, you should clearly understand of your IO library, some of libraries contain segments of pad ring metal and pins for abutment, some of libraries do not. In case if your IO library does not require pad ring routing, you need only to fill all windows in you io ring to avoid any discountinious (gaps). So, when you will dump GDS you should see discountinous metal rings over whole io ring (please donot forget to paste io corner cells).
In case if you IO library requires pad ring routing, it is not a problem as S-route allows to do it easily and painless.
You should understand that s-route can connent some prepeared Power Structures (such as Core ring, Block rings, Stripes and etc) but cannot create them.
If you are interested I could attach my last project scripts:
snapRoute
source SCRIPTS/createDDLRing.tcl
source SCRIPTS/createPLLRing.tcl
source SCRIPTS/routePLL.tcl
source SCRIPTS/createCoreRing.tcl
source SCRIPTS/routeCoreRing.tcl
## split all IO wires
#source SCRIPTS/splitIOWires.tcl
source SCRIPTS/createCoreStripes.tcl
source SCRIPTS/routeCore.tcl