Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

adding delay to FDCE flip flop for simulation

Status
Not open for further replies.
Y

yuvalkesi

Member level 5
Joined
May 13, 2009
Messages
92
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,036
Well, the title practically says it all...
I need to simulate a chain of FF's (FDCE in Xilinx) and for that to be as real as possible I want to add the delay (the dalay is crucial for the simulation). Where is the FDCE code in which I will insert an 'after 1ns' clause?
Or maybe you have another idea?
Thx!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top