gvenki2u
Newbie level 4
Hello,
I am planning to use axi_ahb interface IP in edk ,Since i have a ahb slave with me. So i started a new project in PlanAhead and added new Embedded processor. Then added axi_ahb IP to the BSB and generated the netlist and gone back to Planahead and generated top HDL source .then instantiated my slave to the top file.
I have to access a register which is mapped to slave. To verify the functionality i connected the register value to 8 LEds. My question is
1) since there are no o/ps from ahb slave, except LEDs i changed the o/ps of generated top file.(pull out LEDs) and removed the ahb_master ports in my top module
2) coming to ucf file i added the LED ports to the ucf file.
but the above process is not working on the board. can any one help me.
The bit file generation is fine.but LEDs doesnt work.
regards
venkatesh
I am planning to use axi_ahb interface IP in edk ,Since i have a ahb slave with me. So i started a new project in PlanAhead and added new Embedded processor. Then added axi_ahb IP to the BSB and generated the netlist and gone back to Planahead and generated top HDL source .then instantiated my slave to the top file.
I have to access a register which is mapped to slave. To verify the functionality i connected the register value to 8 LEds. My question is
1) since there are no o/ps from ahb slave, except LEDs i changed the o/ps of generated top file.(pull out LEDs) and removed the ahb_master ports in my top module
2) coming to ucf file i added the LED ports to the ucf file.
but the above process is not working on the board. can any one help me.
The bit file generation is fine.but LEDs doesnt work.
regards
venkatesh