acessing a binary string from a test bench input and storing a part of it in an array

[chat]

hi i am not able to make a program on how to access data from a given input test bench and store particular bits in an array.
ex..
suppose the binary string is 128 bits long 1000111110000111000010101..... & i want to access the bit from 4th pos. till 8 th pos. and store it in an array
what should i do. ?:roll:

 

[TrickyDicky]

what language are you using?

 

[chat]

vhdl..in xilinx

 

[TrickyDicky]

where is the string stored? is it an actual string type, or is it in a text file?

 

[chat]

the string is stored in a test bench. it is actual string

 

[TrickyDicky]

I take it you have something like this?

constant input : string := "0101010......";

then you will need a function to convert the characters to std_logic, something like this:

function string_to_slv( s : string ) return std_logic_vector is
  variable ret_slv : std_logic_vector(s'range);
begin
  for i in s'range loop
    case s(i) is
      when 'U' => ret_slv <= 'U';
      when 'X' => ret_slv <= 'X';
      when '0' => ret_slv <= '0';
      --etc - make sure you cover all cases
      when others => report s(i) & "is not a valid std_logic_value" severity failure;
        
    end case;
  end loop;
  
  return ret_slv;
end function string_to_slv;

my_slv <= string_to_slv( some_string(4 to 8) );

 

[chat]

it's an advanced program ...i need at beginner level...i have made something like this please make the modifications it's not running
entity mywork is
Port ( sentence : in STD_LOGIC_vector(111 downto 0);
testut STD_LOGIC_vector);
end mywork;

architecture Behavioral of mywork is
type arr1 is array(0 to 16)of std_logic ;
variable a1:arr1;
begin

process(sentence)
variable u:integer;
begin

for u in 64 downto 48 loop
arr1 (u-48) <= sentence(u);

end loop;
end Behavioral;

---------- Post added at 14:36 ---------- Previous post was at 14:34 ----------

its..
arr1 (u-48 ) <= sentence(u);

 

[TrickyDicky]

you said you had a string, I dont see any string in your code, just std_logic_vectors

Also, I would advise you never make your own array of std_logic. std_logic_vector is an array of std_logic. It will cause all sorts of problems.

 

[chat]

the string is given in the test bench..it has to be fetched from there..
thanx in advance

 

[TrickyDicky]

entity mywork is
Port ( sentence : in STD_LOGIC_vector(111 downto 0);
       test:out STD_LOGIC_vector);
end mywork;

architecture Behavioral of mywork is
  signal arr1 : std_logic_vector(0 to 16);  --you cannot have variables in an architecture
begin

  process(sentence)
    --you dont need to declare u as a variable
  begin
  
    for u in 64 downto 48 loop
      arr1 (u-48 ) <= sentence(u);
    end loop;
  
  end process;

end Behavioral;

---------- Post added at 11:11 ---------- Previous post was at 11:11 ----------

Please post the test bench code. (please use the code tags)

 

[chat]

actually the string will be generated from a diff. program and will be displayed in the test bench (this is not my part.. it will be done by some one) . my aim is only to fetch data from there and process it accordingly.

 

[TrickyDicky]

are you writing the testbench? if not, then you just need to provide them with this code, and make them do the conversion from string to std_logic_vector

 

[chat]

the test bench is


ENTITY TB12 IS
END TB12;

ARCHITECTURE behavior OF TB12 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT phrase
PORT(
ParseFinalMt : IN std_logic_vector(215 downto 0);
Temp:inout std_logic_vector(7 downto 0);
test_else:inout integer;
test_else1:inout integer;
test_else2:inout integer;
test_else3:inout integer;
test_else_verb:inout integer;
test_else1_verb:inout integer;
test_else2_verb:inout integer;
test_else3_verb:inout integer;
test_rem: INOUT integer;
in_test1:inout integer;
in_test2:inout integer;
in_test3:inout integer;
in_test1_verb:inout integer;
in_test2_verb:inout integer;
in_test3_verb:inout integer;
test_endstm_verb:inout integer;

in_bit : INOUT integer;
in_bit1 : INOUT integer;
in_bit2 : INOUT integer;
in_bit3 : INOUT integer;
test_endstm:inout integer;
in_bitParse: INOUT integer;
test_verb: inout integer;
stored :inout storage;
level1_test:inout integer;
Noun_Verb_Pharse_Level1 : INOUT st1;
test_counter:inout integer;
Noun_Phrase_level1 : INOUT st3;
Verb_Phrase_level2 : INOUT st5;
Verb_main_level2 : INOUT st7
);
END COMPONENT;


--Inputs
signal ParseFinalMt : std_logic_vector(215 downto 0) := (others => '0');
signal Temp : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal test_counter:integer;
signal test_endstm:integer;
signal test_else:integer;
signal test_else1:integer;
signal test_else2:integer;
signal test_else3:integer;
signal test_else_verb:integer;
signal test_else1_verb:integer;
signal test_else2_verb:integer;
signal test_else3_verb:integer;
signal test_rem: integer;
signal in_test1:integer;
signal in_test2: integer;
signal in_test3: integer;

signal in_test1_verb:integer;
signal in_test2_verb: integer;
signal in_test3_verb: integer;

signal in_bit : integer;
signal level1_test:integer;
signal in_bit1 : integer;
signal in_bit2 : integer;
signal in_bit3 : integer;
signal in_bitParse: integer;
signal Noun_Verb_Pharse_Level1 : st1;
signal Noun_Phrase_level1 : st3;
signal Verb_Phrase_level2 : st5;
signal Verb_main_level2 : st7;
signal test_verb:integer;
signal test_endstm_verb:integer;
signal stored:storage;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: phrase PORT MAP (
ParseFinalMt => ParseFinalMt,
test_rem=>test_rem,
test_else=>test_else,
test_counter=>test_counter,
in_test1=>in_test1,
in_test1_verb=>in_test1_verb,
test_else_verb=>test_else_verb,
test_else1_verb=>test_else1_verb,
test_else2_verb=>test_else2_verb,
test_else3_verb=>test_else3_verb,
test_else1=>test_else1,
test_else2=>test_else2,
test_else3=>test_else3,
test_endstm=>test_endstm,
in_test2=>in_test2,
in_test3=>in_test3,
in_test2_verb=>in_test2_verb,
in_test3_verb=>in_test3_verb,
in_bit => in_bit,
in_bit1 => in_bit1,
in_bit2 => in_bit2,
in_bit3 => in_bit3,
level1_test=>level1_test,
test_verb=>test_verb,
test_endstm_verb=>test_endstm_verb,
in_bitParse=> in_bitParse,
Noun_Verb_Pharse_Level1 => Noun_Verb_Pharse_Level1,
Noun_Phrase_level1 => Noun_Phrase_level1,
Verb_Phrase_level2 => Verb_Phrase_level2,
Verb_main_level2 => Verb_main_level2,
Temp=> Temp
);

-- -- Clock process definitions
-- <clock>_process rocess
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.



--
-- NP VP2 PP1
--DTp^my#159#[human]#merA
--Ncns^friend#65#[relative];[thing]#miwra:m 6;miwra:m 6
--CC1^and#151#[]#Ora
--PRPss^i#163#[human]#mEM
--Aux4^are#156#[]#hEM
--VBG^going#81#[],[],[],[],[]#jA:3
--Prep^to#14#[]#H1
--Ncns^paris#46#[place]#perisa:m 8
--~

wait for 100 ns; -- 95-- --
ParseFinalMt<="100000101001010110000000000010101010101101011110011011010111100100100011100111110010001101111010001000110100011011001010000010101011100101011110011000010111001001100101001000111001110000100011111111110111111010111001";
--wait for <clock>_period*10;

-- insert stimulus here

wait;
end process;

END;

 

[TrickyDicky]

they need to instantiate your entity inside the testbench.

 

[chat]

in ur program where the output is displayed ??

---------- Post added at 14:48 ---------- Previous post was at 14:47 ----------

it will be gr8 if u could provide me with the complete program.

 

[TrickyDicky]

what program - like I said, you have to instantiate entities inside a testbench for them to run in simulation.

 

[chat]

how to do that ?

 

[TrickyDicky]

my_work_inst : entity work.mywork
port map (
  sentence => some_slv,
  test => some_other_signal
);

 

[chat]

in this program where the o/p will be displayed.

 

[TrickyDicky]

are you trying to run a simulation, or trying to run it on a real peice of hardware.

Either way, the testbench code you posted cannot work. the phrase component has loads of inout ports of type integer, and you cannot have an inout port of type integer because it is not resolved, and it will fail when you try and simulate it.