sadhika_inti
Newbie level 4
how to define a component in package? please give the syntax for package for component!!!! i have got an error in the package body for jk flip flop in the line underlined below:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 package body strucpkg is entity jkflp is---- i got parse error with this line port(j,k,clk,set,clr:in std_logic; q: buffer std_logic); end jkflp; architecture jk of jkflp is begin process(clk,set,clr) begin if(clr='0') then q<= '0'; elsif (set='0') then q<='1'; elsif falling_edge(clk) then q<= (not(j) and not(k) and q) or (j and not(k)) or (j and k and not(q)); end if; end process; end jk; end jk; end strucpkg;
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