About verilog compile

[liujingshu]

verilog compiler explanation

Hi,all
Our company assign me to stimulate(use Modelsim) and compile(use Design compiler) a code. The stimulation is not very difficult, but compiled is not easy, for it is my first compile job. I can say the code is not very good, for most of module can pass the gate netlist stimulation(without timing information, sdf file) but can not pass the timing stimulation(gate netlist and sdf file). Up to now, my only method is change the code. Fortunately, I correct most of them, but one of them is much bigger, it is not very easy to change. Does have and other method to deal with this problem? May be to set the constraint, but I don't how. May be somebody can give some tips. Thanks very much!!

 

[khorram]

You mean simulation by using Modelsim and synthesis by using DesignCompiler. If you write your code in a standard manner, you will not have major problems. I recommend you to write your code in a standard way in which you separate combinational and sequential parts based on Huff-man model of a digital design.
By the way, timing verifiation is the most important phase of synthesis. You should check the functionality and timing after synthesis. Also you should check them after layout generation. In this phase you extract a netlist (function) and a SDF (timing). You can simulate your design including timing by using a simulator like Modelsim.

RGDS,
KH

 

[liujingshu]

Thank you very much! But I can't understand what's the meaning of "separate combinational and sequential parts based on Huff-man model ", can you give me some explanation, I am still a new code writer. I find there are so many counter in this module, I doubt the problem is here.

 

[khorram]

Suppose you want to implement a hardware that includes combinational and sequential (Flip-Flops or Registers) parts. First of all, you should specify these parts. I mean you should know different parts of your design exactly. In your design, you will have four groups of signals: Primary_Input_Signals (PI); Primary_Output_Signals (PO); Present_state_Signals (PS); Next_State_Signals(NS).
You partition your design to three parts:
1) PO = Output_Function(PI, PS); (in Mealy Model)
PO = Output_Function(PS); (in Moore Model)
2) NS = Next_State_Function(PI, PS);
3) On rising/falling edge of CLOCK: PS <= NS;

I recommand you to see the following link:
https://www.asic-world.com/verilog/memory_fsm2.html

RGDS
KH

 

[Nandy]

I think your situation is
1. RTL sim passes.
2. Gate sim with no timing passes.
3. Gate sim with timing (SDF backannotate) fails.

To Do:
1. You should make sure no timing violation in DC report.
2. Debug your netlist with SDF backannotated, check if there is any timing violation report in simulation report file.
3. Compare all top module inputs waveform in timing/none timing. Make sure they are the same.
4. If you want dig through netlist with SDF file. Use GOF from www.nandigits.com
GOF can load netlist and SDF file, and isolate the gates you have interest in, and even report the timing between connections and gate delay.

Hope it helps.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

Added after 13 minutes:

I think your situation is
1. RTL sim passes.
2. Gate sim with no timing passes.
3. Gate sim with timing (SDF backannotate) fails.

To Do:
1. You should make sure no timing violation in DC report.
2. Debug your netlist with SDF backannotated, check if there is any timing violation report in simulation report file.
3. Compare all top module inputs waveform in timing/none timing. Make sure they are the same.
4. If you want dig through netlist with SDF file. Use GOF from www.nandigits.com
GOF can load netlist and SDF file, and isolate the gates you have interest in, and even report the timing between connections and gate delay.

Hope it helps.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.