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about transmission gates

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Newbie level 6
Jun 4, 2011
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i am designing discrete time OTA. In this design i am using transmission gate as a switch.
i have doubt about the bulk of transmission gate. where i have to connect bulk of nmost,and pmost in transmission gate.
if anybody knows please give reply.

connect each to their respective sources. That way there will be no body effect

In an N-well process you have no choice, body of NMOS transistors is tied to the P-Substrate, however, substrate of PMOS transistors can be attached to any potential as 'analogTechie' recommended.

You would need a twin-tub process in order to get both transistors' sources and substrates, respectively, connected together.

in a triple well process can i short the source and body of a transistor irrespective of wherever it is in the stack right?

Dear 'chandra3789', it looks like we missed the 'discrete' part in the original question posted by 'Ramakrishna47'. So first, lets answer his question. Ramakrishna47, as a rule of thumb, the substrate of an NMOs transistor must be tied to the lowest potential of all other pins (gate, source, drain) in the same transistor -not necesarily GND- in order to ensure parasitics p-n junctions always be inverted. In a similar way, the substrate of a PMOS transistor must be tied to the highest potential of all other pins in the same transistor -not necesarily VDD-.
Please, do not believe me, try it yourself with a simulation using simple models.

And 'chandra3789', as you have noticed, you simply shoud ensure parasitics p-n junctions do not get activated.

if i short source and body of a MOS the parasitic p-n junction willl be zero biased which means it is not activated....but since different sources of diff transistors will have diff voltages and body must be the same(in n-well process) we cannot short them in n-well process...but in triple well process each MOS will have its own local body and hence i can connect the source and body together.......
plz correct me if i am wrong

thanks g2marco.i have understood your it possible leave bulk terminals as a floating terminal?
if it is not what are the problems tell to me.

'Ramakrishna47', CMOS trasnsistor depends on well defined potentials in all of their terminals. By leaving a terminal floating, behavior is unpredectible at best no operation at worst.

'chandra3789', just remember that drain and source share the same substrate, so simply take care of not polarizing directly any of the two p-n juctions.

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