about the link and uniquify commands in design compiler

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ASIC_intl

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design compiler uniquify

Hi

I have two separate question as shown below.

1. I am using design compiler in Tcl mode for synthesis. When I am writing the file necessary for synthesis at the begining I an setting the search_path, link_library and target_library variables.

Then I am reading all the verilog files (netlists) by the read_verilog command. After that I am setting the current_design. Then I am writing the uniquify command. Is it important to write the uniquify command for synthesis.

2. After the uniquify command in the above file (as described in question No. 1) I am writing the link command. Is it important to write the link command while doing synthesis? Can I do the synthesis without the link command? The above file (as described in question No. 1) also contains other necessary commands for synthesis after the link command.

Thanks,
ASIC
 

design compiler link


uniquify command is used to generate separate instances within the netlist... It is used before importing the list to place and route tool.... Never miss this command...

link command is not a mandatory one... This command is used when you are translating some netlist from one technology to another, so target library is the new library and the link library is the original one....It can also be used while doing timing analysis...So not a mandatory requirement for synthesis....Tool might give you a warning due to missing link_library, but you can safely ignore it.....
 

uniquify design compiler

uniquify command need not be used if you are using the latest version of DC, it does uniquify automatically and at the appropriate time, though not at the point of time it would do if you had the command in your script as it is now. If you ar using an older version it is a good practice to use uniquify as suggested in the other reply to your post.

It is recommended to use the link command. You can do synthesis without a link command, since the commands that follow the link command in a typical script, like compile etc, will do an automatic linking!

- Prasad.


Added after 3 minutes:

The link command is used to resolve all the references in the design being syntheisized. I think you cannot ignore a link_library missing warning. Since the tool will not synthesize the module that it could not link. Let me know if you think I am wrong.

- Prasad.

 

uniquify list in tcl


Nope... You can synthesize if you don't have link_library available. It can be problematic if you are doing some analysis, like timing, or power. And also if you have some black box available like memories, etc.
You are saying that the tool will not synthesize if the module could not be linked...My question is why do you want to link if you don't have any netlist available beforehand??
So let me explain it further, if you have a design in which few of the blocks are already synthesized and some of the blocks are RTL, then use link command, if not and whole of the design is RTL(verilog or VHDL) and nothing technology specific then there is no need to have link command....
If you still have further doubts then don't hesitate to ask...

“Often, we are too slow to recognize how much and in what ways we can assist each other through sharing such expertise and knowledge.”
 

what is uniquify

what if i need to simulate the design on the gtech level...do i need to make uniquify as well??
 

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