about the checking of code

[kannan2590]

below is the code in vhdl for polyphase filters and the different components inside polyphase are the subfilters.The question is whether this is a good programming practice or is it better to use for generate statements.Also is this code good on implementing on fpga .Is for generate statements good for more than 20 coefficients.

for polyphase

---

Code VHDL - [expand]
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library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_SIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
 library UNISIM;
 use UNISIM.VComponents.all;
 
entity polyphase is
 Port ( clk : in STD_LOGIC;
 
clk_120mbps: in std_logic;
 reset : in STD_LOGIC;
 din : in STD_LOGIC_vector(7 downto 0);
 ifiltout : out STD_LOGIC_vector(23 downto 0)
 );
 end polyphase;
 
architecture Behavioral of polyphase is
 
component subfilta
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltb
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltc
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltd
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ----
 component subfilte
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
--
 component subfiltf
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
---- 
component subfiltg
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 -- 
component subfilth
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfilti
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltj
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltk
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltl
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltm
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ------
 component subfiltn
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
--
 component subfilto
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
-- 
component subfiltp
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltq
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltr
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfilts
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltt
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ----
 component subfiltu
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
--
 component subfiltv
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
-- 
component subfiltw
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 -- 
component subfiltx
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfilty
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltz
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 
component subfiltaa
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltbb
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ---- 
component subfiltcc
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component;
 ----
 component subfiltdd
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
--
 component subfiltee
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
-- 
component subfiltff
 port( dout:out std_logic_vector(23 downto 0);
 clk:in std_logic;
 
reset:in std_logic;
 din:in std_logic_vector(7 downto 0)
 );
 end component; 
 
 
signal ifilterout0,ifilterout1,ifilterout2,ifilterout3:ST D_LOGIC_vector(23 downto 0):=(others =>'0');
 signal ifilterout4,ifilterout5,ifilterout6,ifilterout7:ST D_LOGIC_vector(23 downto 0):=(others =>'0');
 
signal ifilterout8,ifilterout9,ifilterout10,ifilterout11: STD_LOGIC_vector(23 downto 0):=(others =>'0');
 signal ifilterout12,ifilterout13,ifilterout14,ifilterout1 5:STD_LOGIC_vector(23 downto 0):=(others =>'0');
 
signal ifilterout16,ifilterout17,ifilterout18,ifilterout1 9:STD_LOGIC_vector(23 downto 0):=(others =>'0');
 signal ifilterout20,ifilterout21,ifilterout22,ifilterout2 3:STD_LOGIC_vector(23 downto 0):=(others =>'0');
 
signal ifilterout24,ifilterout25,ifilterout26,ifilterout2 7:STD_LOGIC_vector(23 downto 0):=(others =>'0');
 signal ifilterout28,ifilterout29,ifilterout30,ifilterout3 1:STD_LOGIC_vector(23 downto 0):=(others =>'0');
 --
 
begin
 subfilt0a: subfilta port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout0);
 subfilt0b: subfiltb port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout1);
 subfilt0c: subfiltc port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout2);
 subfilt0d: subfiltd port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout3);
 subfilt0e: subfilte port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout4);
 subfilt0f: subfiltf port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout5);
 subfilt0g: subfiltg port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout6);
 subfilt0h: subfilth port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout7);
 
subfilt0i: subfilti port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout8);
 subfilt0j: subfiltj port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout9);
 subfilt0k: subfiltk port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout10);
 subfilt0l: subfiltl port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout11);
 subfilt0m: subfiltm port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout12);
 subfilt0n: subfiltn port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout13);
 subfilt0o: subfilto port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout14);
 subfilt0p: subfiltp port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout15);
 
subfilt0q: subfiltq port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout16);
 subfilt0r: subfiltr port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout17);
 subfilt0s: subfilts port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout18);
 subfilt0t: subfiltt port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout19);
 subfilt0u: subfiltu port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout20);
 subfilt0v: subfiltv port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout21);
 subfilt0w: subfiltw port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout22);
 subfilt0x: subfiltx port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout23);
 
subfilt0y: subfilty port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout24);
 subfilt0z: subfiltz port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout25);
 subfilt0aa: subfiltaa port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout26);
 subfilt0bb: subfiltbb port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout27);
 subfilt0cc: subfiltcc port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout28);
 subfilt0dd: subfiltdd port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout29);
 subfilt0ee: subfiltee port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout30);
 subfilt0ff: subfiltff port map( Reset=> Reset, Clk=>Clk, din => din, dout => ifilterout31);
 
--
 P20:PROCESS(clk_120mbps,RESET)
 VARIABLE CNT:STD_LOGIC_VECTOR(5 DOWNTO 0):="000000";
 BEGIN
 
 
IF RESET='0' THEN
 CNT:="000000";
 ifiltout <=(others =>'0');
 ELSIF clk_120mbps='1' AND clk_120mbps'EVENT THEN
 CNT := CNT +1;
 CASE CNT IS 
WHEN "000001"=> ifiltout <=ifilterout0;
 WHEN "000010"=> ifiltout <=ifilterout1;
 WHEN "000011"=> ifiltout <=ifilterout2;
 WHEN "000100"=> ifiltout <=ifilterout3;
 WHEN "000101"=> ifiltout <=ifilterout4;
 WHEN "000110"=> ifiltout <=ifilterout5;
 
WHEN "000111"=> ifiltout <=ifilterout6;
 WHEN "001000"=> ifiltout <=ifilterout7;
 
WHEN "001001"=> ifiltout <=ifilterout8;
 WHEN "001010"=> ifiltout <=ifilterout9;
 WHEN "001011"=> ifiltout <=ifilterout10;
 WHEN "001100"=> ifiltout <=ifilterout11;
 WHEN "001101"=> ifiltout <=ifilterout12;
 WHEN "001110"=> ifiltout <=ifilterout13;
 ---- 
WHEN "001111"=> ifiltout <=ifilterout14;
 WHEN "010000"=> ifiltout <=ifilterout15;
 
WHEN "010001"=> ifiltout <=ifilterout16;
 WHEN "010010"=> ifiltout <=ifilterout17;
 WHEN "010011"=> ifiltout <=ifilterout18;
 WHEN "010100"=> ifiltout <=ifilterout19;
 WHEN "010101"=> ifiltout <=ifilterout20;
 WHEN "010110"=> ifiltout <=ifilterout21;
 
WHEN "010111"=> ifiltout <=ifilterout22;
 WHEN "011000"=> ifiltout <=ifilterout23;
 
WHEN "011001"=> ifiltout <=ifilterout24;
 WHEN "011010"=> ifiltout <=ifilterout25;
 WHEN "011011"=> ifiltout <=ifilterout26;
 WHEN "011100"=> ifiltout <=ifilterout27;
 WHEN "011101"=> ifiltout <=ifilterout28;
 WHEN "011110"=> ifiltout <=ifilterout29;
 
WHEN "011111"=> ifiltout <=ifilterout30;
 WHEN "100000"=> ifiltout <=ifilterout31;
 -- 
 
-- 
CNT := "000000";
 
WHEN OTHERS => ifiltout <="000000000000000000000000";
 END CASE;
 --CNT <= CNT +1;
 END IF;
 END PROCESS P20;
 
 
 
end Behavioral;

---

for subfilta

---

Code VHDL - [expand]
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library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_SIGNED.ALL;
 
 
---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;
 
entity subfilta is
 Port ( dout : out STD_LOGIC_vector(23 downto 0);
 clk : in STD_LOGIC;
 
reset : in STD_LOGIC;
 din : in STD_LOGIC_vector(7 downto 0));
 end subfilta;
 
architecture Behavioral of subfilta is
 
--component DFF is 
-- port(
 -- q : out STD_LOGIC_vector(27 downto 0); --output connected to the adder
 -- Clk :in std_logic; -- Clock input
 -- d :in STD_LOGIC_vector(27 downto 0) -- Data input from the MCM block.
 -- );
 --end component; 
 
component DFFa is 
port(
 q : out STD_LOGIC_vector(7 downto 0); --output connected to the adder
 Clk :in std_logic; -- Clock input
 d :in STD_LOGIC_vector(7 downto 0) -- Data input from the MCM block.
 );
 end component; 
 
 
 
signal H00,H032,H064 : STD_LOGIC_vector(15 downto 0) := (others => '0');
 --signal MCM00,MCM01,MCM02,MCM03 : STD_LOGIC_vector(31 downto 0) := (others => '0');
 signal add_out01: STD_LOGIC_vector(23 downto 0) := (others => '0');
 --signal Q01,Q02,Q03 : STD_LOGIC_vector(31 downto 0) := (others => '0');
 signal din1,din2:std_logic_vector(7 downto 0):=(others =>'0');
 --signal Q0100 : STD_LOGIC_vector(27 downto 0) := (others => '0');
 --signal Q01000 : STD_LOGIC_vector(27 downto 0) := (others => '0');
 begin
 
H00 <= "1111110110101011";
 
H032<= "0011111010011010";
 
H064<= "0000001100010010";
 
add_out01 <=(din*H00)+(din1*H032)+(din2*H064);
 
dffaa : DFFa port map(q=>din1,clk=>clk,d=>din);
 dffbb : DFFa port map(q=>din2,clk=>clk,d=>din1);
 
 
 
p01000:process(Clk,reset)
 begin
 if reset='0' then
 dout <= "000000000000000000000000";
 elsif clk'event and clk='1' then
 
dout <= add_out01;
 
end if;
 end process p01000;
 
 
 
end Behavioral;
 
 
about DFFA
 
library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_SIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;
 
entity DFFa is
 Port ( Q : out std_logic_vector(7 downto 0);
 CLK : in STD_LOGIC;
 
D : in std_logic_vector(7 downto 0));
 end DFFa;
 
architecture Behavioral of DFFa is
 
 
signal qt1 : std_logic_vector(7 downto 0) := (others => '0');
 
begin 
 
Q <= qt1;
 --
 p10:process(Clk)
 begin 
if ( rising_edge(Clk) ) then 
qt1 <= D; 
end if; 
 
 
 
 
end process p10; 
 
 
 
end Behavioral;

---

 

[TrickyDicky]

yuck - pretty hideous code.

Using a few arrays and the like you could probably cut the whole lot down to <50 lines of code. Why are the DFFs their own component? why not just make a DFF in a process?
Why have you got 30+ components that probably do the same thing? yes you should use a for..generate.

 

[ads_ee]

He's probably got so many of the sub-filters because each one has different coefficients...should make one sub-filter with parameterized coefficients.

 

[mrflibble]

My eyes!!! @_@

May I suggest using for generate?

 

[kannan2590]

My eyes!!! @_@

May I suggest using for generate?

Can you suggest me for the use of for generate statement. Actually i am avoiding the for generate statement because 96 coefficients polyphase filter the fpga system will become slow. Again if you have any idea from the given code you please write the the code which i have written using for generate statement .But different subfilters have different coefficients. Again tell me what is the meaning of parameterized coefficients

 

[TrickyDicky]

I highly suggest a VHDL tutorial. or a good VHDL reference manual.

The Doulos Golden reference guide for VHDL is great (but its not for learning VHDL from).

 

[mrflibble]

Again if you have any idea from the given code you please write the the code which i have written using for generate statement .But different subfilters have different coefficients. Again tell me what is the meaning of parameterized coefficients

Sure. Just send me your billing address.

make a module for the sub-filters. make an array with the coefficients in them. make a for generate that instantiates the parameterized modules based on the coefficients in the parameter array. It should do the same as your very loooooooong piece of code, but then suddenly be more readable.

 

[kannan2590]

Sure. Just send me your billing address.

make a module for the sub-filters. make an array with the coefficients in them. make a for generate that instantiates the parameterized modules based on the coefficients in the parameter array. It should do the same as your very loooooooong piece of code, but then suddenly be more readable.

please can you do the same thing with your own example with 96 coefficients using for genearate statement.Actually the coefficients is from coe file and it is 16 bit wide and in hexadecimal representation.Actually on coefficient i can give you as an example is ffee in hexadecimal.like this you can create your own 96 coefficients in hexadecimal format arbitrarily and tell me how to write for generate statement and tell me howmake an array with the coefficients .Can you please write the code and tell me the meaning of parameterized modules based on the coefficients in the parameter array by writing the code please.

 

[mrflibble]

... tell me how to write for generate statement and tell me howmake an array with the coefficients ...

I suggest you:
1 - read a vhdl book of your choice
2 - try a few examples
3 - rewrite your current code in the manner suggested in previous posts
4 - profit!

 

[kannan2590]

I suggest you:
1 - read a vhdl book of your choice
2 - try a few examples
3 - rewrite your current code in the manner suggested in previous posts
4 - profit!

Actually i can read books but i am in lack of time so i please suggest you to do as i have written in the previous post.i have read the books and i know the for generate statement but from your side please explain me the thing with a code

 

[mrflibble]

Actually i can read books but i am in lack of time so i please suggest you to do as i have written in the previous post.i have read the books and i know the for generate statement but from your side please explain me the thing with a code

There we go, some example code using for generate: https://vhdlguru.blogspot.nl/2010/09/how-to-use-generate-keyword-for.html

 

[kannan2590]

He's probably got so many of the sub-filters because each one has different coefficients...should make one sub-filter with parameterized coefficients.

Is this you expected from me.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;


entity filter10 is
Port ( clk : in STD_LOGIC;

clk_120mbps: in std_logic;
reset : in STD_LOGIC;
din : in STD_LOGIC_vector(7 downto 0);
ifiltout : out STD_LOGIC_vector(23 downto 0)
);
end filter10;

architecture Behavioral of filter10 is

signal H00,H032,H064 : STD_LOGIC_vector(15 downto 0) := (others => '0');

signal MCM00, add_out01, add_out02,MCM01, MCM02: STD_LOGIC_vector(23 downto 0) := (others => '0');


--signal Q01,Q02,Q03 : STD_LOGIC_vector(31 downto 0) := (others => '0');
signal Q1,Q2:std_logic_vector(23 downto 0):=(others =>'0');



begin
P20ROCESS(clk,RESET)
VARIABLE CNT:STD_LOGIC_VECTOR(5 DOWNTO 0):="000000";
BEGIN


IF RESET='0' THEN
CNT:="000000";
add_out02<="000000000000000000000000";
ELSIF clk='1' AND clk'EVENT THEN


CNT := CNT +1;
CASE CNT IS
WHEN "000001"=> H00 <= "1111111110101011";
H032<= "0011111010011011";
H064<= "0000001100000010";


WHEN "000010"=> H00 <= "0111110100100100";
H032<= "0100000111111101";
H064<= "0000000100001111";


WHEN "000011"=> H00 <= "1011110010011111";
H032<= "0100010100000111";
H064<= "1111111101011000";


WHEN "000100"=> H00 <= "1111110000100001";
H032<= "0100011110101100";
H064<= "1111110111110001";


WHEN "000101"=> H00 <= "1011101110101101";
H032<= "0100100111100110";
H064<= "1111110011010011";



WHEN "000110"=> H00 <= "1011101101001100";
H032<= "0100101110101110";
H064<= "1111101111111011";


WHEN "000111"=> H00 <= "0111101100000011";
H032<= "0100110011110101";
H064<= "1111101101100000";


WHEN "001000"=> H00 <= "1011101011011010";
H032<= "0100110110111010";
H064<= "1111101100000011";

WHEN "001001"=> H00 <= "1011101011010111";
H032<= "0100110111111100";
H064<= "1111101011010110";


WHEN "001010"=> H00 <= "1011101100000010";
H032<= "0100110110111010";
H064<= "1111101011011011";


WHEN "001011"=> H00 <= "1011101101100000";
H032<= "0100110011110101";
H064<= "1111101100000010";


WHEN "001100"=> H00 <= "1011101111111001";
H032<= "0100101110101101";
H064<= "1111101101001101";


WHEN "001101"=> H00 <= "1011110011010010";
H032<= "0100100111100101";
H064<= "1111101110101111";


WHEN "001110"=>H00 <= "0111110111110000";
H032<= "0100011110101101";
H064<= "1111110000100001";

----
WHEN "001111"=> H00 <= "0111111101011001";
H032<= "0100010100000111";
H064<= "1111110010011110";


WHEN "010000"=> H00 <= "0100000100001111";
H032<= "0100000111111101";
H064<= "1111110100100101";


WHEN "010001"=> H00 <= "0100001100010010";
H032<= "0011111010011011";
H064<= "1111110110101010";


WHEN "010010"=> H00 <= "0100010101100110";
H032<= "0011101011101111";
H064<= "1000000000000000";



WHEN "010011"=> H00 <= "0000100000001001";
H032<= "0011011100000011";
H064<= "0100000000000000";


WHEN "010100"=> H00 <= "0000101011111000";
H032<= "0011001011100111";
H064<= "1000000000000000";


WHEN "010101"=> H00 <= "0000111000110011";
H032<= "0010111010101111";
H064<= "1000000000000000";



WHEN "010110"=> H00 <= "0001000110101110";
H032<= "0010101001010110";
H064<= "0000000001000000";


WHEN "010111"=> H00 <= "1001010101101010";
H032<= "0010010111111110";
H064<= "0000000000000001";



WHEN "011000"=> H00 <= "0101010101101010";
H032<= "0010010111111111";
H064<= "0000000100000000";


WHEN "011001"=> H00 <= "0001110101110100";
H032<= "0001110101101100";
H064<= "0100000000000000";


WHEN "011010"=> H00 <= "0010000110101001";
H032<= "0001100101011010";
H064<= "1000000000000000";


WHEN "011011"=> H00 <= "0010010111111101";
H032<= "0001010101101011";
H064<= "1000000000000000";


WHEN "011100"=> H00 <= "0010101001010110";
H032<= "0001000110101101";
H064<= "0000000000000001";


WHEN "011101"=> H00 <= "0110111010101000";
H032<= "0000111000110110";
H064<= "1000000000000000";


WHEN "011110"=> H00 <= "0011001011101010";
H032<= "0000101011111010";
H064<= "0000000010000000";


WHEN "011111"=> H00 <= "0111011100000010";
H032<= "0000100000001101";
H064<= "0110000000000000";


WHEN "100000"=> H00 <= "0011101011101100";
H032<= "0000010101100100";
H064<= "0000000000000010";

--
CNT := "000000";
when others => H00 <= "0000000000000000";
H032<= "0000000000000000";
H064<= "0000000000000000";


END CASE;
--CNT <= CNT +1;
END IF;
END PROCESS P20;

P40ROCESS(clk,RESET)
BEGIN
IF RESET='0' THEN

Q1<="000000000000000000000000";
Q2<="000000000000000000000000";
ELSIF clk'EVENT AND clk='1' THEN


MCM00 <= (din*H064);
MCM01 <= (din*H032);
MCM02 <= (din*H00);
add_out01 <= Q1+MCM01;
add_out02 <= Q2+MCM02;
Q1<=MCM00;
Q2<=add_out01;

END IF;
END PROCESS P40;

According to the code for each count values we have different values of H00,H032,H064.So If i want to use the values of H00,H032,H064 for every count value and assign it to Multiplication with din and assign it to MCM00,MCM01,MCM02 .How to do it can you explain it to me now?

 

[kannan2590]

He's probably got so many of the sub-filters because each one has different coefficients...should make one sub-filter with parameterized coefficients.

can you explain with vhdl code to make one sub-filter with parameterized coefficients.