In PrimeTime:
set link_library "your_lib.db" # specify your synopsys libraries
read_verilog ... # read your gate-level netlist
link
read_parasitics ... # read parasitics of interconnecting wires (derived from Place'n'Route tool, or manually create it, or skip this step)
read_sdc ... # read timing constraints (clock frequency etc)
report_timing ... # to see the critical pathes
write_spice_deck -header header.inc -sub_circuit_file library.spi -output output.sp [get_timing_path -from ... -to ...]
# header.inc should contains at least hspice statements like ".lib <model.lib>"
# library.spi should contains spice (transistor-level) netlist for each gates of your gate-level netlist
# output.sp is the final spice runset
Then, run Hspice
hspice output.sp
Then look in the *.mt0 file, that Hspice have generated. It will contains measurement results for all gates in your critical path, cell delay and transition time. The measurements named like delay_inv1/a_inv1/z, which means, that it is delay from pin inv1/a to pin inv1/z. You should find the same measurement in the PrimeTime timing report. If digits are equal (almost), it is good
. If differs - how big difference - it is not good