lhlbluesky
Banned
i have designed a adc of 10bit 1.5bit per stage,but when i simulate it,i find that the output of mdac(from the second stage)settles very slowly,while when i simulate each stage seperately,it has no problem.what's the possible reason?
besides,how to decide the driving ability of clock generator?and how to enhance the driving ability of clock generator?i use cascaded inverters with increasing W/L,is that ok?to improve the driving ability,can i increase the number of cascaded inverters?
pls help me.
besides,how to decide the driving ability of clock generator?and how to enhance the driving ability of clock generator?i use cascaded inverters with increasing W/L,is that ok?to improve the driving ability,can i increase the number of cascaded inverters?
pls help me.