about pipelined adc,ergent

[lhlbluesky]

i have designed a adc of 10bit 1.5bit per stage,but when i simulate it,i find that the output of mdac(from the second stage)settles very slowly,while when i simulate each stage seperately,it has no problem.what's the possible reason?
besides,how to decide the driving ability of clock generator?and how to enhance the driving ability of clock generator?i use cascaded inverters with increasing W/L,is that ok?to improve the driving ability,can i increase the number of cascaded inverters?
pls help me.

 

[rfsystem]

Is there a interleaving in the sample/radix operation between successive stage? Otherwise the settling goes through the hole pipeline.

Or is the reference cell loaded and all pipeline cells couple together?

 

[lhlbluesky]

any other advice,pls?

 

[jeffsky520]

hi please describe in detail your question,
anyway, I think, the problem maybe exists at OP AMP capacitance driving and timing .

 

[ljy4468]

when You simulate each state seperately, you said it's ok.
Then, Did you simulate each stage separately with modeled load capacitor?
capacitor like comparator cap, sampling cap, switch cap... of the next stage.

And you can calculate whole switch's gate capacitance of entire stage. And you can use clock gen with inverter buffer with adequate size.

Regards.

 

[lhlbluesky]

thanks for all reply.
what's the proper size for transgate?3/1 for nmos is ok?
besides,i use a voltage reference to generate the three reference for my adc,and i find that the three reference voltages settles slowly(about half the effective clock phase of phi1 and phi2);i think maybe this is the problem,but when i increase the GBW of the buffer of the three reference signals(voltage reference: resistor ladder followed by three buffers),it improves a little only;how to improve the settling of reference voltage?
pls give me some advice.thanks again.